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2440addr.h
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1 //=============================================================================
2 // File Name : 2440addr.h
3 // Function : S3C2440 Define Address Register
4 // History
5 // 0.0 : Programming start (February 15,2002) -> SOP
6 // Revision : 03.11.2003 ver 0.0 Attatched for 2440
7 //=============================================================================
8 
9 #ifndef __2440ADDR_H__
10 #define __2440ADDR_H__
11 
12 #ifdef __cplusplus
13 extern "C" {
14 #endif
15 
16 #include "option.h"
17 
18 
19 // Memory control
20 #define rBWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status
21 #define rBANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control
22 #define rBANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control
23 #define rBANKCON2 (*(volatile unsigned *)0x4800000c) //BANK2 cControl
24 #define rBANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control
25 #define rBANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control
26 #define rBANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control
27 #define rBANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control
28 #define rBANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control
29 #define rREFRESH (*(volatile unsigned *)0x48000024) //DRAM/SDRAM refresh
30 #define rBANKSIZE (*(volatile unsigned *)0x48000028) //Flexible Bank Size
31 #define rMRSRB6 (*(volatile unsigned *)0x4800002c) //Mode register set for SDRAM
32 #define rMRSRB7 (*(volatile unsigned *)0x48000030) //Mode register set for SDRAM
33 
34 
35 // USB Host
36 
37 
38 // INTERRUPT
39 #define rSRCPND (*(volatile unsigned *)0x4a000000) //Interrupt request status
40 #define rINTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control
41 #define rINTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control
42 #define rPRIORITY (*(volatile unsigned *)0x4a00000c) //IRQ priority control
43 #define rINTPND (*(volatile unsigned *)0x4a000010) //Interrupt request status
44 #define rINTOFFSET (*(volatile unsigned *)0x4a000014) //Interruot request source offset
45 #define rSUBSRCPND (*(volatile unsigned *)0x4a000018) //Sub source pending
46 #define rINTSUBMSK (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask
47 
48 
49 // DMA
50 #define rDISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source
51 #define rDISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control
52 #define rDIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination
53 #define rDIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control
54 #define rDCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control
55 #define rDSTAT0 (*(volatile unsigned *)0x4b000014) //DMA 0 Status
56 #define rDCSRC0 (*(volatile unsigned *)0x4b000018) //DMA 0 Current source
57 #define rDCDST0 (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination
58 #define rDMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger
59 
60 #define rDISRC1 (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source
61 #define rDISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control
62 #define rDIDST1 (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination
63 #define rDIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control
64 #define rDCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control
65 #define rDSTAT1 (*(volatile unsigned *)0x4b000054) //DMA 1 Status
66 #define rDCSRC1 (*(volatile unsigned *)0x4b000058) //DMA 1 Current source
67 #define rDCDST1 (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination
68 #define rDMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger
69 
70 #define rDISRC2 (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source
71 #define rDISRCC2 (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control
72 #define rDIDST2 (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination
73 #define rDIDSTC2 (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control
74 #define rDCON2 (*(volatile unsigned *)0x4b000090) //DMA 2 Control
75 #define rDSTAT2 (*(volatile unsigned *)0x4b000094) //DMA 2 Status
76 #define rDCSRC2 (*(volatile unsigned *)0x4b000098) //DMA 2 Current source
77 #define rDCDST2 (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination
78 #define rDMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger
79 
80 #define rDISRC3 (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source
81 #define rDISRCC3 (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control
82 #define rDIDST3 (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination
83 #define rDIDSTC3 (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control
84 #define rDCON3 (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control
85 #define rDSTAT3 (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status
86 #define rDCSRC3 (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source
87 #define rDCDST3 (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination
88 #define rDMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger
89 
90 
91 // CLOCK & POWER MANAGEMENT
92 #define rLOCKTIME (*(volatile unsigned *)0x4c000000) //PLL lock time counter
93 #define rMPLLCON (*(volatile unsigned *)0x4c000004) //MPLL Control
94 #define rUPLLCON (*(volatile unsigned *)0x4c000008) //UPLL Control
95 #define rCLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control
96 #define rCLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control
97 #define rCLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control
98 #define rCAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control
99 
100 
101 // LCD CONTROLLER
102 #define rLCDCON1 (*(volatile unsigned *)0x4d000000) //LCD control 1
103 #define rLCDCON2 (*(volatile unsigned *)0x4d000004) //LCD control 2
104 #define rLCDCON3 (*(volatile unsigned *)0x4d000008) //LCD control 3
105 #define rLCDCON4 (*(volatile unsigned *)0x4d00000c) //LCD control 4
106 #define rLCDCON5 (*(volatile unsigned *)0x4d000010) //LCD control 5
107 #define rLCDSADDR1 (*(volatile unsigned *)0x4d000014) //STN/TFT Frame buffer start address 1
108 #define rLCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2
109 #define rLCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set
110 #define rREDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table
111 #define rGREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table
112 #define rBLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table
113 #define rDITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode
114 #define rTPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette
115 #define rLCDINTPND (*(volatile unsigned *)0x4d000054) //LCD Interrupt pending
116 #define rLCDSRCPND (*(volatile unsigned *)0x4d000058) //LCD Interrupt source
117 #define rLCDINTMSK (*(volatile unsigned *)0x4d00005c) //LCD Interrupt mask
118 #define rTCONSEL (*(volatile unsigned *)0x4d000060) //LPC3600 Control --- edited by junon
119 #define PALETTE 0x4d000400 //Palette start address
120 
121 
122 //Nand Flash
123 #define rNFCONF (*(volatile unsigned *)0x4E000000) //NAND Flash configuration
124 #define rNFCONT (*(volatile unsigned *)0x4E000004) //NAND Flash control
125 #define rNFCMD (*(volatile unsigned *)0x4E000008) //NAND Flash command
126 #define rNFADDR (*(volatile unsigned *)0x4E00000C) //NAND Flash address
127 #define rNFDATA (*(volatile unsigned *)0x4E000010) //NAND Flash data
128 #define rNFDATA8 (*(volatile unsigned char *)0x4E000010) //NAND Flash data
129 #define NFDATA (0x4E000010) //NAND Flash data address
130 #define rNFMECCD0 (*(volatile unsigned *)0x4E000014) //NAND Flash ECC for Main Area
131 #define rNFMECCD1 (*(volatile unsigned *)0x4E000018)
132 #define rNFSECCD (*(volatile unsigned *)0x4E00001C) //NAND Flash ECC for Spare Area
133 #define rNFSTAT (*(volatile unsigned *)0x4E000020) //NAND Flash operation status
134 #define rNFESTAT0 (*(volatile unsigned *)0x4E000024)
135 #define rNFESTAT1 (*(volatile unsigned *)0x4E000028)
136 #define rNFMECC0 (*(volatile unsigned *)0x4E00002C)
137 #define rNFMECC1 (*(volatile unsigned *)0x4E000030)
138 #define rNFSECC (*(volatile unsigned *)0x4E000034)
139 #define rNFSBLK (*(volatile unsigned *)0x4E000038) //NAND Flash Start block address
140 #define rNFEBLK (*(volatile unsigned *)0x4E00003C) //NAND Flash End block address
141 
142 
143 //Camera Interface
144 #define rASIZE (*(volatile unsigned *)0x4F000000)
145 #define rSTAY1 (*(volatile unsigned *)0x4F000004)
146 #define rSTAY2 (*(volatile unsigned *)0x4F000008)
147 #define rSTAY3 (*(volatile unsigned *)0x4F00000C)
148 #define rSTAY4 (*(volatile unsigned *)0x4F000010)
149 #define rAYBURST (*(volatile unsigned *)0x4F000014)
150 #define rACBBURST (*(volatile unsigned *)0x4F000018)
151 #define rACRBURST (*(volatile unsigned *)0x4F00001C)
152 #define rBSIZE (*(volatile unsigned *)0x4F000020)
153 #define rSTBY1 (*(volatile unsigned *)0x4F000024)
154 #define rSTBY2 (*(volatile unsigned *)0x4F000028)
155 #define rSTBY3 (*(volatile unsigned *)0x4F00002C)
156 #define rSTBY4 (*(volatile unsigned *)0x4F000030)
157 #define rBYBURST (*(volatile unsigned *)0x4F000034)
158 #define rBCBBURST (*(volatile unsigned *)0x4F000038)
159 #define rBCRBURST (*(volatile unsigned *)0x4F00003C)
160 #define rADISTWIDTH (*(volatile unsigned *)0x4F000040)
161 #define rBDISTWIDTH (*(volatile unsigned *)0x4F000044)
162 #define rYRATIO (*(volatile unsigned *)0x4F00004C)
163 #define rCRATIO (*(volatile unsigned *)0x4F000050)
164 #define rYORIGINAL (*(volatile unsigned *)0x4F000054)
165 #define rCORIGINAL (*(volatile unsigned *)0x4F00005C)
166 #define rSTACB1 (*(volatile unsigned *)0x4F000074)
167 #define rSTACB2 (*(volatile unsigned *)0x4F000078)
168 #define rSTACB3 (*(volatile unsigned *)0x4F00007C)
169 #define rSTACB4 (*(volatile unsigned *)0x4F000080)
170 #define rSTACR1 (*(volatile unsigned *)0x4F000084)
171 #define rSTACR2 (*(volatile unsigned *)0x4F000088)
172 #define rSTACR3 (*(volatile unsigned *)0x4F00008C)
173 #define rSTACR4 (*(volatile unsigned *)0x4F000090)
174 #define rSTBCB1 (*(volatile unsigned *)0x4F00009C)
175 #define rSTBCB2 (*(volatile unsigned *)0x4F0000A0)
176 #define rSTBCB3 (*(volatile unsigned *)0x4F0000A4)
177 #define rSTBCB4 (*(volatile unsigned *)0x4F0000A8)
178 #define rSTBCR1 (*(volatile unsigned *)0x4F0000AC)
179 #define rSTBCR2 (*(volatile unsigned *)0x4F0000B0)
180 #define rSTBCR3 (*(volatile unsigned *)0x4F0000B4)
181 #define rSTBCR4 (*(volatile unsigned *)0x4F0000B8)
182 #define rCTRL_C (*(volatile unsigned *)0x4F0000BC)
183 // read only register
184 #define rRDSTAT (*(volatile unsigned *)0x4F000000)
185 #define rRDSTAY (*(volatile unsigned *)0x4F000014)
186 #define rRDSTACB (*(volatile unsigned *)0x4F000018)
187 #define rRDSTACR (*(volatile unsigned *)0x4F00001C)
188 #define rRDSTACB1 (*(volatile unsigned *)0x4F000020)
189 #define rRDSTACR1 (*(volatile unsigned *)0x4F000024)
190 #define rRDSTBY1 (*(volatile unsigned *)0x4F000028)
191 #define rRDSTBY2 (*(volatile unsigned *)0x4F00002C)
192 #define rRDSTBY3 (*(volatile unsigned *)0x4F000030)
193 #define rRDSTBY4 (*(volatile unsigned *)0x4F000034)
194 #define rRDSTBY (*(volatile unsigned *)0x4F000038)
195 #define rRDSTBCB (*(volatile unsigned *)0x4F00003C)
196 #define rRDSTBCR (*(volatile unsigned *)0x4F000040)
197 #define rRDSTBCB1 (*(volatile unsigned *)0x4F000044)
198 #define rRDSTBCR1 (*(volatile unsigned *)0x4F000048)
199 #define rRDADISTWIDTH (*(volatile unsigned *)0x4F00004C)
200 #define rRDBDISTWIDTH (*(volatile unsigned *)0x4F000050)
201 
202 
203 // UART
204 #define rULCON0 (*(volatile unsigned *)0x50000000) //UART 0 Line control
205 #define rUCON0 (*(volatile unsigned *)0x50000004) //UART 0 Control
206 #define rUFCON0 (*(volatile unsigned *)0x50000008) //UART 0 FIFO control
207 #define rUMCON0 (*(volatile unsigned *)0x5000000c) //UART 0 Modem control
208 #define rUTRSTAT0 (*(volatile unsigned *)0x50000010) //UART 0 Tx/Rx status
209 #define rUERSTAT0 (*(volatile unsigned *)0x50000014) //UART 0 Rx error status
210 #define rUFSTAT0 (*(volatile unsigned *)0x50000018) //UART 0 FIFO status
211 #define rUMSTAT0 (*(volatile unsigned *)0x5000001c) //UART 0 Modem status
212 #define rUBRDIV0 (*(volatile unsigned *)0x50000028) //UART 0 Baud rate divisor
213 
214 #define rULCON1 (*(volatile unsigned *)0x50004000) //UART 1 Line control
215 #define rUCON1 (*(volatile unsigned *)0x50004004) //UART 1 Control
216 #define rUFCON1 (*(volatile unsigned *)0x50004008) //UART 1 FIFO control
217 #define rUMCON1 (*(volatile unsigned *)0x5000400c) //UART 1 Modem control
218 #define rUTRSTAT1 (*(volatile unsigned *)0x50004010) //UART 1 Tx/Rx status
219 #define rUERSTAT1 (*(volatile unsigned *)0x50004014) //UART 1 Rx error status
220 #define rUFSTAT1 (*(volatile unsigned *)0x50004018) //UART 1 FIFO status
221 #define rUMSTAT1 (*(volatile unsigned *)0x5000401c) //UART 1 Modem status
222 #define rUBRDIV1 (*(volatile unsigned *)0x50004028) //UART 1 Baud rate divisor
223 #define rULCON2 (*(volatile unsigned *)0x50008000) //UART 2 Line control
224 #define rUCON2 (*(volatile unsigned *)0x50008004) //UART 2 Control
225 #define rUFCON2 (*(volatile unsigned *)0x50008008) //UART 2 FIFO control
226 #define rUMCON2 (*(volatile unsigned *)0x5000800c) //UART 2 Modem control
227 #define rUTRSTAT2 (*(volatile unsigned *)0x50008010) //UART 2 Tx/Rx status
228 #define rUERSTAT2 (*(volatile unsigned *)0x50008014) //UART 2 Rx error status
229 #define rUFSTAT2 (*(volatile unsigned *)0x50008018) //UART 2 FIFO status
230 #define rUMSTAT2 (*(volatile unsigned *)0x5000801c) //UART 2 Modem status
231 #define rUBRDIV2 (*(volatile unsigned *)0x50008028) //UART 2 Baud rate divisor
232 
233 #ifdef __BIG_ENDIAN
234 #define rUTXH0 (*(volatile unsigned char *)0x50000023) //UART 0 Transmission Hold
235 #define rURXH0 (*(volatile unsigned char *)0x50000027) //UART 0 Receive buffer
236 #define rUTXH1 (*(volatile unsigned char *)0x50004023) //UART 1 Transmission Hold
237 #define rURXH1 (*(volatile unsigned char *)0x50004027) //UART 1 Receive buffer
238 #define rUTXH2 (*(volatile unsigned char *)0x50008023) //UART 2 Transmission Hold
239 #define rURXH2 (*(volatile unsigned char *)0x50008027) //UART 2 Receive buffer
240 
241 #define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
242 #define RdURXH0() (*(volatile unsigned char *)0x50000027)
243 #define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
244 #define RdURXH1() (*(volatile unsigned char *)0x50004027)
245 #define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
246 #define RdURXH2() (*(volatile unsigned char *)0x50008027)
247 
248 #define UTXH0 (0x50000020+3) //Byte_access address by DMA
249 #define URXH0 (0x50000024+3)
250 #define UTXH1 (0x50004020+3)
251 #define URXH1 (0x50004024+3)
252 #define UTXH2 (0x50008020+3)
253 #define URXH2 (0x50008024+3)
254 
255 #else //Little Endian
256 #define rUTXH0 (*(volatile unsigned char *)0x50000020) //UART 0 Transmission Hold
257 #define rURXH0 (*(volatile unsigned char *)0x50000024) //UART 0 Receive buffer
258 #define rUTXH1 (*(volatile unsigned char *)0x50004020) //UART 1 Transmission Hold
259 #define rURXH1 (*(volatile unsigned char *)0x50004024) //UART 1 Receive buffer
260 #define rUTXH2 (*(volatile unsigned char *)0x50008020) //UART 2 Transmission Hold
261 #define rURXH2 (*(volatile unsigned char *)0x50008024) //UART 2 Receive buffer
262 
263 #define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
264 #define RdURXH0() (*(volatile unsigned char *)0x50000024)
265 #define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
266 #define RdURXH1() (*(volatile unsigned char *)0x50004024)
267 #define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
268 #define RdURXH2() (*(volatile unsigned char *)0x50008024)
269 
270 #define UTXH0 (0x50000020) //Byte_access address by DMA
271 #define URXH0 (0x50000024)
272 #define UTXH1 (0x50004020)
273 #define URXH1 (0x50004024)
274 #define UTXH2 (0x50008020)
275 #define URXH2 (0x50008024)
276 #endif
277 
278 
279 // PWM TIMER
280 #define rTCFG0 (*(volatile unsigned *)0x51000000) //Timer 0 configuration
281 #define rTCFG1 (*(volatile unsigned *)0x51000004) //Timer 1 configuration
282 #define rTCON (*(volatile unsigned *)0x51000008) //Timer control
283 #define rTCNTB0 (*(volatile unsigned *)0x5100000c) //Timer count buffer 0
284 #define rTCMPB0 (*(volatile unsigned *)0x51000010) //Timer compare buffer 0
285 #define rTCNTO0 (*(volatile unsigned *)0x51000014) //Timer count observation 0
286 #define rTCNTB1 (*(volatile unsigned *)0x51000018) //Timer count buffer 1
287 #define rTCMPB1 (*(volatile unsigned *)0x5100001c) //Timer compare buffer 1
288 #define rTCNTO1 (*(volatile unsigned *)0x51000020) //Timer count observation 1
289 #define rTCNTB2 (*(volatile unsigned *)0x51000024) //Timer count buffer 2
290 #define rTCMPB2 (*(volatile unsigned *)0x51000028) //Timer compare buffer 2
291 #define rTCNTO2 (*(volatile unsigned *)0x5100002c) //Timer count observation 2
292 #define rTCNTB3 (*(volatile unsigned *)0x51000030) //Timer count buffer 3
293 #define rTCMPB3 (*(volatile unsigned *)0x51000034) //Timer compare buffer 3
294 #define rTCNTO3 (*(volatile unsigned *)0x51000038) //Timer count observation 3
295 #define rTCNTB4 (*(volatile unsigned *)0x5100003c) //Timer count buffer 4
296 #define rTCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4
297 
298 
299 // USB DEVICE
300 #ifdef __BIG_ENDIAN
301 <ERROR IF BIG_ENDIAN>
302 #define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address
303 #define rPWR_REG (*(volatile unsigned char *)0x52000147) //Power management
304 #define rEP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear
305 #define rUSB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear
306 #define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable
307 #define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016f)
308 #define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte
309 #define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte
310 #define rINDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index
311 #define rMAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet
312 #define rEP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status
313 #define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status
314 #define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018b)
315 #define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status
316 #define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197)
317 #define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count
318 #define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f)
319 #define rEP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO
320 #define rEP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO
321 #define rEP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO
322 #define rEP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO
323 #define rEP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO
324 #define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control
325 #define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter
326 #define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter
327 #define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter
328 #define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213)
329 #define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217)
330 #define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control
331 #define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter
332 #define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter
333 #define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter
334 #define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b)
335 #define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f)
336 #define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control
337 #define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter
338 #define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter
339 #define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter
340 #define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253)
341 #define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257)
342 #define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control
343 #define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter
344 #define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter
345 #define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter
346 #define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b)
347 #define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f)
348 
349 #else // Little Endian
350 #define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address
351 #define rPWR_REG (*(volatile unsigned char *)0x52000144) //Power management
352 #define rEP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear
353 #define rUSB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear
354 #define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable
355 #define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016c)
356 #define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte
357 #define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte
358 #define rINDEX_REG (*(volatile unsigned char *)0x52000178) //Register index
359 #define rMAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet
360 #define rEP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status
361 #define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status
362 #define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188)
363 #define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status
364 #define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194)
365 #define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count
366 #define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c)
367 #define rEP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO
368 #define rEP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO
369 #define rEP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO
370 #define rEP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO
371 #define rEP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO
372 #define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control
373 #define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter
374 #define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter
375 #define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter
376 #define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210)
377 #define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214)
378 #define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control
379 #define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter
380 #define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter
381 #define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter
382 #define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228)
383 #define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c)
384 #define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control
385 #define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter
386 #define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter
387 #define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter
388 #define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250)
389 #define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254)
390 #define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control
391 #define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter
392 #define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter
393 #define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter
394 #define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268)
395 #define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c)
396 #endif // __BIG_ENDIAN
397 
398 
399 // WATCH DOG TIMER
400 #define rWTCON (*(volatile unsigned *)0x53000000) //Watch-dog timer mode
401 #define rWTDAT (*(volatile unsigned *)0x53000004) //Watch-dog timer data
402 #define rWTCNT (*(volatile unsigned *)0x53000008) //Eatch-dog timer count
403 
404 
405 // IIC
406 #define rIICCON (*(volatile unsigned *)0x54000000) //IIC control
407 #define rIICSTAT (*(volatile unsigned *)0x54000004) //IIC status
408 #define rIICADD (*(volatile unsigned *)0x54000008) //IIC address
409 #define rIICDS (*(volatile unsigned *)0x5400000c) //IIC data shift
410 #define rIICLC (*(volatile unsigned *)0x54000010) //IIC multi-master line control
411 
412 
413 // IIS
414 #define rIISCON (*(volatile unsigned *)0x55000000) //IIS Control
415 #define rIISMOD (*(volatile unsigned *)0x55000004) //IIS Mode
416 #define rIISPSR (*(volatile unsigned *)0x55000008) //IIS Prescaler
417 #define rIISFCON (*(volatile unsigned *)0x5500000c) //IIS FIFO control
418 #ifdef __BIG_ENDIAN
419  #define rIISFIFO (*(volatile unsigned short *)0x55000012) //IIS FIFO entry
420 #else //Little Endian
421  #define rIISFIFO (*(volatile unsigned short *)0x55000010) //IIS FIFO entry
422 #endif
423 #ifdef __BIG_ENDIAN
424 #define IISFIFO ((volatile unsigned short *)0x55000012) //IIS FIFO entry
425 #else //Little Endian
426 #define IISFIFO ((volatile unsigned short *)0x55000010) //IIS FIFO entry
427 #endif
428 
429 
430 // I/O PORT
431 #define rGPACON (*(volatile unsigned *)0x56000000) //Port A control
432 #define rGPADAT (*(volatile unsigned *)0x56000004) //Port A data
433 
434 #define rGPBCON (*(volatile unsigned *)0x56000010) //Port B control
435 #define rGPBDAT (*(volatile unsigned *)0x56000014) //Port B data
436 #define rGPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B
437 
438 #define rGPCCON (*(volatile unsigned *)0x56000020) //Port C control
439 #define rGPCDAT (*(volatile unsigned *)0x56000024) //Port C data
440 #define rGPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C
441 
442 #define rGPDCON (*(volatile unsigned *)0x56000030) //Port D control
443 #define rGPDDAT (*(volatile unsigned *)0x56000034) //Port D data
444 #define rGPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D
445 
446 #define rGPECON (*(volatile unsigned *)0x56000040) //Port E control
447 #define rGPEDAT (*(volatile unsigned *)0x56000044) //Port E data
448 #define rGPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E
449 
450 #define rGPFCON (*(volatile unsigned *)0x56000050) //Port F control
451 #define rGPFDAT (*(volatile unsigned *)0x56000054) //Port F data
452 #define rGPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F
453 
454 #define rGPGCON (*(volatile unsigned *)0x56000060) //Port G control
455 #define rGPGDAT (*(volatile unsigned *)0x56000064) //Port G data
456 #define rGPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G
457 
458 #define rGPHCON (*(volatile unsigned *)0x56000070) //Port H control
459 #define rGPHDAT (*(volatile unsigned *)0x56000074) //Port H data
460 #define rGPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H
461 
462 #define rGPJCON (*(volatile unsigned *)0x560000d0) //Port J control
463 #define rGPJDAT (*(volatile unsigned *)0x560000d4) //Port J data
464 #define rGPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J
465 
466 #define rMISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control
467 #define rDCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control
468 #define rEXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control register 0
469 #define rEXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control register 1
470 #define rEXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control register 2
471 #define rEINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved
472 #define rEINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved
473 #define rEINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control register 2
474 #define rEINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control register 3
475 #define rEINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask
476 #define rEINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending
477 #define rGSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status
478 #define rGSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32440000)
479 #define rGSTATUS2 (*(volatile unsigned *)0x560000b4) //Reset type
480 #define rGSTATUS3 (*(volatile unsigned *)0x560000b8) //Saved data0(32-bit) before entering POWER_OFF mode
481 #define rGSTATUS4 (*(volatile unsigned *)0x560000bc) //Saved data0(32-bit) before entering POWER_OFF mode
482 
483 // Added for 2440
484 #define rFLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only)
485 #define rDSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0
486 #define rDSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1
487 #define rMSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register
488 
489 // RTC
490 #ifdef __BIG_ENDIAN
491 #define rRTCCON (*(volatile unsigned char *)0x57000043) //RTC control
492 #define rTICNT (*(volatile unsigned char *)0x57000047) //Tick time count
493 #define rRTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control
494 #define rALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second
495 #define rALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute
496 #define rALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour
497 #define rALMDATE (*(volatile unsigned char *)0x57000063) //Alarm date //edited by junon
498 #define rALMMON (*(volatile unsigned char *)0x57000067) //Alarm month
499 #define rALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year
500 #define rRTCRST (*(volatile unsigned char *)0x5700006f) //RTC round reset
501 #define rBCDSEC (*(volatile unsigned char *)0x57000073) //BCD second
502 #define rBCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute
503 #define rBCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour
504 #define rBCDDATE (*(volatile unsigned char *)0x5700007f) //BCD date //edited by junon
505 #define rBCDDAY (*(volatile unsigned char *)0x57000083) //BCD day //edited by junon
506 #define rBCDMON (*(volatile unsigned char *)0x57000087) //BCD month
507 #define rBCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year
508 
509 #else //Little Endian
510 #define rRTCCON (*(volatile unsigned char *)0x57000040) //RTC control
511 #define rTICNT (*(volatile unsigned char *)0x57000044) //Tick time count
512 #define rRTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control
513 #define rALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second
514 #define rALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute
515 #define rALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour
516 #define rALMDATE (*(volatile unsigned char *)0x57000060) //Alarm date // edited by junon
517 #define rALMMON (*(volatile unsigned char *)0x57000064) //Alarm month
518 #define rALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year
519 #define rRTCRST (*(volatile unsigned char *)0x5700006c) //RTC round reset
520 #define rBCDSEC (*(volatile unsigned char *)0x57000070) //BCD second
521 #define rBCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute
522 #define rBCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour
523 #define rBCDDATE (*(volatile unsigned char *)0x5700007c) //BCD date //edited by junon
524 #define rBCDDAY (*(volatile unsigned char *)0x57000080) //BCD day //edited by junon
525 #define rBCDMON (*(volatile unsigned char *)0x57000084) //BCD month
526 #define rBCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year
527 #endif //RTC
528 
529 
530 // ADC
531 #define rADCCON (*(volatile unsigned *)0x58000000) //ADC control
532 #define rADCTSC (*(volatile unsigned *)0x58000004) //ADC touch screen control
533 #define rADCDLY (*(volatile unsigned *)0x58000008) //ADC start or Interval Delay
534 #define rADCDAT0 (*(volatile unsigned *)0x5800000c) //ADC conversion data 0
535 #define rADCDAT1 (*(volatile unsigned *)0x58000010) //ADC conversion data 1
536 #define rADCUPDN (*(volatile unsigned *)0x58000014) //Stylus Up/Down interrupt status
537 
538 
539 // SPI
540 #define rSPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control
541 #define rSPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status
542 #define rSPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control
543 #define rSPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud rate prescaler
544 #define rSPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data
545 #define rSPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data
546 
547 #define rSPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control
548 #define rSPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status
549 #define rSPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control
550 #define rSPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud rate prescaler
551 #define rSPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data
552 #define rSPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data
553 
554 
555 // SD Interface
556 #define rSDICON (*(volatile unsigned *)0x5a000000) //SDI control
557 #define rSDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud rate prescaler
558 #define rSDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument
559 #define rSDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control
560 #define rSDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status
561 #define rSDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI response 0
562 #define rSDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI response 1
563 #define rSDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI response 2
564 #define rSDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI response 3
565 #define rSDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer
566 #define rSDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size
567 #define rSDIDCON (*(volatile unsigned *)0x5a00002c) //SDI data control
568 #define rSDIDCNT (*(volatile unsigned *)0x5a000030) //SDI data remain counter
569 #define rSDIDSTA (*(volatile unsigned *)0x5a000034) //SDI data status
570 #define rSDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status
571 #define rSDIIMSK (*(volatile unsigned *)0x5a000040) //SDI interrupt mask
572 
573 #ifdef __BIG_ENDIAN
574 #define rSDIDAT (*(volatile unsigned *)0x5a00003f) //SDI data
575 #define SDIDAT 0x5a00003f
576 #else // Little Endian
577 #define rSDIDAT (*(volatile unsigned *)0x5a00003c) //SDI data
578 #define SDIDAT 0x5a00003c
579 #endif //SD Interface
580 
581 
582 // Exception vector
583 #define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
584 #define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
585 #define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
586 #define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xc))
587 #define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
588 #define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
589 #define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
590 #define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1c))
591 // Interrupt vector
592 #define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
593 #define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
594 #define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
595 #define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2c))
596 #define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
597 #define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
598 #define pISR_CAM (*(unsigned *)(_ISR_STARTADDRESS+0x38)) // Added for 2440.
599 #define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3c))
600 #define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
601 #define pISR_WDT_AC97 (*(unsigned *)(_ISR_STARTADDRESS+0x44))
602 #define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
603 #define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4c))
604 #define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
605 #define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
606 #define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
607 #define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5c))
608 #define pISR_LCD (*(unsigned *)(_ISR_STARTADDRESS+0x60))
609 #define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
610 #define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
611 #define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6c))
612 #define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
613 #define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74))
614 #define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
615 #define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7c))
616 #define pISR_NFCON (*(unsigned *)(_ISR_STARTADDRESS+0x80)) // Added for 2440.
617 #define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
618 #define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
619 #define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8c))
620 #define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
621 #define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
622 #define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
623 #define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0x9c))
624 
625 
626 // PENDING BIT
627 #define BIT_EINT0 (0x1)
628 #define BIT_EINT1 (0x1<<1)
629 #define BIT_EINT2 (0x1<<2)
630 #define BIT_EINT3 (0x1<<3)
631 #define BIT_EINT4_7 (0x1<<4)
632 #define BIT_EINT8_23 (0x1<<5)
633 #define BIT_CAM (0x1<<6) // Added for 2440.
634 #define BIT_BAT_FLT (0x1<<7)
635 #define BIT_TICK (0x1<<8)
636 #define BIT_WDT_AC97 (0x1<<9)
637 #define BIT_TIMER0 (0x1<<10)
638 #define BIT_TIMER1 (0x1<<11)
639 #define BIT_TIMER2 (0x1<<12)
640 #define BIT_TIMER3 (0x1<<13)
641 #define BIT_TIMER4 (0x1<<14)
642 #define BIT_UART2 (0x1<<15)
643 #define BIT_LCD (0x1<<16)
644 #define BIT_DMA0 (0x1<<17)
645 #define BIT_DMA1 (0x1<<18)
646 #define BIT_DMA2 (0x1<<19)
647 #define BIT_DMA3 (0x1<<20)
648 #define BIT_SDI (0x1<<21)
649 #define BIT_SPI0 (0x1<<22)
650 #define BIT_UART1 (0x1<<23)
651 #define BIT_NFCON (0x1<<24) // Added for 2440.
652 #define BIT_USBD (0x1<<25)
653 #define BIT_USBH (0x1<<26)
654 #define BIT_IIC (0x1<<27)
655 #define BIT_UART0 (0x1<<28)
656 #define BIT_SPI1 (0x1<<29)
657 #define BIT_RTC (0x1<<30)
658 #define BIT_ADC (0x1<<31)
659 #define BIT_ALLMSK (0xffffffff)
660 
661 #define BIT_SUB_ALLMSK (0x7fff)
662 #define BIT_SUB_AC97 (0x1<<14)
663 #define BIT_SUB_WDT (0x1<<13)
664 #define BIT_SUB_CAM_S (0x1<<12) // Added for 2440.
665 #define BIT_SUB_CAM_C (0x1<<11) // Added for 2440.
666 #define BIT_SUB_ADC (0x1<<10)
667 #define BIT_SUB_TC (0x1<<9)
668 #define BIT_SUB_ERR2 (0x1<<8)
669 #define BIT_SUB_TXD2 (0x1<<7)
670 #define BIT_SUB_RXD2 (0x1<<6)
671 #define BIT_SUB_ERR1 (0x1<<5)
672 #define BIT_SUB_TXD1 (0x1<<4)
673 #define BIT_SUB_RXD1 (0x1<<3)
674 #define BIT_SUB_ERR0 (0x1<<2)
675 #define BIT_SUB_TXD0 (0x1<<1)
676 #define BIT_SUB_RXD0 (0x1<<0)
677 /*
678 #define ClearPending(bit) {\
679  rSRCPND = bit;\
680  rINTPND = bit;\
681  rINTPND;\
682  }
683 */
684 #define EnableIrq(bit) rINTMSK &= ~(bit)
685 #define DisableIrq(bit) rINTMSK |= (bit)
686 #define EnableSubIrq(bit) rINTSUBMSK &= ~(bit)
687 #define DisableSubIrq(bit) rINTSUBMSK |= (bit)
688 __inline void ClearPending(int bit)
689 {
690  register i;
691  rSRCPND = bit;
692  rINTPND = bit;
693  i = rINTPND;
694 }
695 __inline void ClearSubPending(int bit)
696 {
697  register i;
698  rSUBSRCPND = bit;
699  i = rINTPND;
700 }
701 //Wait until rINTPND is changed for the case that the ISR is very short.
702 
703 
704 #ifdef __cplusplus
705 }
706 #endif
707 #endif //__2440ADDR_H__
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