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Memcfg.inc
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1 ;************************************************
2 ; NAME : MEMCFG.A
3 ; DESC : Memory bank configuration file
4 ; Revision: 02.28.2002 ver 0.0
5 ; Revision: 03.11.2003 ver 0.0 Attatched for 2440
6 ;************************************************
7 
8 ;Memory Area
9 ;GCS6 32bit(64MB) SDRAM(0x3000_0000-0x33ff_ffff)
10 
11 
12 ;BWSCON
13 DW8 EQU (0x0)
14 DW16 EQU (0x1)
15 DW32 EQU (0x2)
16 WAIT EQU (0x1<<2)
17 UBLB EQU (0x1<<3)
18 
19  ASSERT :DEF:BUSWIDTH
20  [ BUSWIDTH=16
21 B1_BWSCON EQU (DW16)
22 B2_BWSCON EQU (DW16)
23 B3_BWSCON EQU (DW16)
24 B4_BWSCON EQU (DW16)
25 B5_BWSCON EQU (DW16)
26 B6_BWSCON EQU (DW16)
27 B7_BWSCON EQU (DW16)
28  | ;BUSWIDTH=32 ; 2440 EV board.
29 B1_BWSCON EQU (DW16) ; AMD flash(AM29LV800B), 16-bit, for nCS1
30 B2_BWSCON EQU (DW16) ; PCMCIA(PD6710), 16-bit
31 B3_BWSCON EQU (DW16 + WAIT + UBLB) ; Ethernet(CS8900), 16-bit, hzh
32 B4_BWSCON EQU (DW16 + WAIT + UBLB) ;Ethernet dm9000 ,16bit,zjx; Intel Strata(28F128), 32-bit, for nCS4
33 B5_BWSCON EQU (DW16) ; A400/A410 Ext, 16-bit
34 B6_BWSCON EQU (DW32) ; SDRAM(K4S561632C) 32MBx2, 32-bit
35 B7_BWSCON EQU (DW32) ; N.C.
36  ]
37 
38 ;BANK0CON
39 
40 B0_Tacs EQU 0x0 ;0clk
41 B0_Tcos EQU 0x1 ;0clk
42 B0_Tacc EQU 0x7 ;14clk
43 B0_Tcoh EQU 0x1 ;0clk
44 B0_Tah EQU 0x0 ;0clk
45 B0_Tacp EQU 0x0
46 B0_PMC EQU 0x0 ;normal
47 
48 ;BANK1CON
49 B1_Tacs EQU 1;0x0 ;0clk
50 B1_Tcos EQU 1;0x0 ;0clk
51 B1_Tacc EQU 6;0x7 ;14clk
52 B1_Tcoh EQU 1;0x0 ;0clk
53 B1_Tah EQU 1;0x0 ;0clk
54 B1_Tacp EQU 0x0
55 B1_PMC EQU 0x0 ;normal
56 
57 ;Bank 2 parameter
58 B2_Tacs EQU 1;0x0 ;0clk
59 B2_Tcos EQU 1;0x0 ;0clk
60 B2_Tacc EQU 6;0x7 ;14clk
61 B2_Tcoh EQU 1;0x0 ;0clk
62 B2_Tah EQU 1;0x0 ;0clk
63 B2_Tacp EQU 0x0
64 B2_PMC EQU 0x0 ;normal
65 
66 ;Bank 3 parameter
67 B3_Tacs EQU 0x1;0 ;0clk
68 B3_Tcos EQU 0x1;0 ;0clk
69 B3_Tacc EQU 0x6;7 ;14clk
70 B3_Tcoh EQU 0x1;0 ;0clk
71 B3_Tah EQU 0x1;0 ;0clk
72 B3_Tacp EQU 0x0
73 B3_PMC EQU 0x0 ;normal
74 
75 ;Bank 4 parameter
76 B4_Tacs EQU 0x1;0 ;0clk
77 B4_Tcos EQU 0x1;0 ;0clk
78 B4_Tacc EQU 0x6;7 ;14clk
79 B4_Tcoh EQU 0x1;0 ;0clk
80 B4_Tah EQU 0x1;0 ;0clk
81 B4_Tacp EQU 0x0
82 B4_PMC EQU 0x0 ;normal
83 
84 ;Bank 5 parameter
85 B5_Tacs EQU 0x1;0 ;0clk
86 B5_Tcos EQU 0x1;0 ;0clk
87 B5_Tacc EQU 0x6;7 ;14clk
88 B5_Tcoh EQU 0x1;0 ;0clk
89 B5_Tah EQU 0x1;0 ;0clk
90 B5_Tacp EQU 0x0
91 B5_PMC EQU 0x0 ;normal
92 
93  [ {TRUE} ; When 100MHz HCLK is used.
94 ;Bank 6 parameter
95 B6_MT EQU 0x3 ;SDRAM
96 B6_Trcd EQU 0x1 ;3clk
97 B6_SCAN EQU 0x1 ;9bit
98 
99 ;Bank 7 parameter
100 B7_MT EQU 0x3 ;SDRAM
101 B7_Trcd EQU 0x1 ;3clk
102 B7_SCAN EQU 0x1 ;9bit
103 
104 ;REFRESH parameter
105 REFEN EQU 0x1 ;Refresh enable
106 TREFMD EQU 0x0 ;CBR(CAS before RAS)/Auto refresh
107 Trp EQU 0x1 ;3clk
108 Tsrc EQU 0x1 ;5clk Trc= Trp(3)+Tsrc(5) = 8clock
109 Tchr EQU 0x2 ;3clk
110 ;REFCNT EQU 1580 ;HCLK=60Mhz, (2048+1-7.81*60) hzh
111 ;REFCNT EQU 1502 ;HCLK=70Mhz, (2048+1-7.81*70) hzh
112 ;REFCNT EQU 1424 ;HCLK=80Mhz, (2048+1-7.81*80) hzh
113 REFCNT EQU 1346 ;HCLK=90Mhz, (2048+1-7.81*90) hzh
114 ;REFCNT EQU 1268 ;HCLK=100Mhz, (2048+1-7.81*100) hzh
115  |
116 ;Bank 6 parameter
117 B6_MT EQU 0x3 ;SDRAM
118 B6_Trcd EQU 0x1 ;4clk
119 B6_SCAN EQU 0x1 ;9bit
120 
121 ;Bank 7 parameter
122 B7_MT EQU 0x3 ;SDRAM
123 B7_Trcd EQU 0x2 ;4clk
124 B7_SCAN EQU 0x1 ;9bit
125 
126 ;REFRESH parameter
127 REFEN EQU 0x1 ;Refresh enable
128 TREFMD EQU 0x0 ;CBR(CAS before RAS)/Auto refresh
129 Trp EQU 0x2 ;4clk
130 Tsrc EQU 0x2 ;6clk Trc= Trp(4)+Tsrc(6) = 10clock
131 
132 Tchr EQU 0x2 ;3clk
133 REFCNT EQU 1012 ;HCLK=135Mhz, (2048+1-7.8*133 = 1012)
134  ]
135 
136  END
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