dm9000a.h

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#ifndef DM9000_H
#define DM9000_H

#define DM9000_ADDRESS 0x19000300
#define DM9000_INDEX   DM9000_ADDRESS
#define DM9000_DATA    (DM9000_ADDRESS+4)
#define DM9000_16BIT

#define DM9000_ID               0x90000a46 // pid+vid
#define DM9000_PKT_MAX  1536       // Received packet max size 
#define DM9000_PKT_RDY  0x01       // Packet ready to receive 

enum DM9000_PHY_MODE{
DM9000_10MHD=0,
DM9000_100MHD=1,
DM9000_10MFD=4,
DM9000_100MFD=5,
DM9000_AUTO=8,
DM9000_1M_HPNA=0x10
};
enum DM9000_LINK_MODE{
DM9000_LINK_10HDX=0,
DM9000_LINK_10FDX=1,
DM9000_LINK_100HDX=2,
DM9000_LINK_100FDX=3,
DM9000_LINK_UNKNOW=4
};
// although the registers are 16 bit, they are 32-bit aligned.
#define DM9000_NCR      0x00
#define DM9000_NSR      0x01
#define DM9000_TCR      0x02
#define DM9000_TSR1     0x03
#define DM9000_TSR2     0x04
#define DM9000_RCR      0x05
#define DM9000_RSR      0x06
#define DM9000_ROCR     0x07
#define DM9000_BPTR     0x08
#define DM9000_FCTR     0x09
#define DM9000_FCR      0x0A
#define DM9000_EPCR     0x0B // eeprom & phy control register
#define DM9000_EPAR     0x0C // eeprom & phy address register
#define DM9000_EPDRL    0x0D
#define DM9000_EPDRH    0x0E
#define DM9000_WCR      0x0F

#define DM9000_PAR      0x10 // physical address register
#define DM9000_MAR      0x16 // multicast address register

#define DM9000_GPCR             0x1e
#define DM9000_GPR      0x1f
#define DM9000_TRPAL    0x22
#define DM9000_TRPAH    0x23
#define DM9000_RWPAL    0x24
#define DM9000_RWPAH    0x25

#define DM9000_VIDL     0x28
#define DM9000_VIDH     0x29
#define DM9000_PIDL     0x2A
#define DM9000_PIDH     0x2B

#define DM9000_CHIPR    0x2C
#define DM9000_SMCR     0x2F

#define DM9000_PHY              0x40    

#define DM9000_MRCMDX   0xF0
#define DM9000_MRCMD    0xF2
#define DM9000_MRRL     0xF4
#define DM9000_MRRH     0xF5
#define DM9000_MWCMDX   0xF6
#define DM9000_MWCMD    0xF8
#define DM9000_MWRL     0xFA
#define DM9000_MWRH     0xFB
#define DM9000_TXPLL    0xFC
#define DM9000_TXPLH    0xFD
#define DM9000_ISR      0xFE
#define DM9000_IMR      0xFF

#define DM9000_PHY_STATUS 0x01
#define     BIT_AUTO_N_COMPL  0x20
#define DM9000_PHY_SCS  0x11  // phy sepecified config status register

#define NCR_EXT_PHY             (1<<7)
#define NCR_WAKEEN              (1<<6)
#define NCR_FCOL                (1<<4)
#define NCR_FDX                 (1<<3)
#define NCR_LBK                 (3<<1)
#define NCR_RST                 (1<<0)

#define NSR_SPEED               (1<<7)
#define NSR_LINKST              (1<<6)
#define NSR_WAKEST              (1<<5)
#define NSR_TX2END              (1<<3)
#define NSR_TX1END              (1<<2)
#define NSR_RXOV                (1<<1)

#define TCR_TJDIS               (1<<6)
#define TCR_EXCECM              (1<<5)
#define TCR_PAD_DIS2    (1<<4)
#define TCR_CRC_DIS2    (1<<3)
#define TCR_PAD_DIS1    (1<<2)
#define TCR_CRC_DIS1    (1<<1)
#define TCR_TXREQ               (1<<0)

#define TSR_TJTO                (1<<7)
#define TSR_LC                  (1<<6)
#define TSR_NC                  (1<<5)
#define TSR_LCOL                (1<<4)
#define TSR_COL                 (1<<3)
#define TSR_EC                  (1<<2)

#define RCR_WTDIS               (1<<6)
#define RCR_DIS_LONG    (1<<5)
#define RCR_DIS_CRC             (1<<4)
#define RCR_ALL                 (1<<3)
#define RCR_RUNT                (1<<2)
#define RCR_PRMSC               (1<<1)
#define RCR_RXEN                (1<<0)

#define RSR_RF                  (1<<7)
#define RSR_MF                  (1<<6)
#define RSR_LCS                 (1<<5)
#define RSR_RWTO                (1<<4)
#define RSR_PLE                 (1<<3)
#define RSR_AE                  (1<<2)
#define RSR_CE                  (1<<1)
#define RSR_FOE                 (1<<0)

#define FCTR_HWOT(ot)   ((ot&0xf)<<4)
#define FCTR_LWOT(ot)   (ot&0xf)

#define IMR_PAR                 (1<<7)
#define IMR_ROOM                (1<<3)
#define IMR_ROM                 (1<<2)
#define IMR_PTM                 (1<<1)
#define IMR_PRM                 (1<<0)

#define DM9000_PACKET_READY 0x01 // packet ready to receive

typedef struct{
    INT8U State;
    INT8U Status;
    INT8U LinkType;
    INT8U InUse;
    INT16U Id;
    INT16U UserId;
    INT16U Timer;
    INT8U InitialPass;
    INT16U RxEvent;
    INT32U IoBase;   
    INT32U MemBase;
    INT8U MacAddress[ETHERNET_MAC_LENGTH];
    INT8U IpAddress[ETHERNET_IP_LENGTH];
}DM9000_CONTROL;

extern DM9000_CONTROL Dm9000Ctrl;
extern void F_Dm9000Init(void);    
extern void F_Dm9000Svc(void);  
extern INT8U F_Dm9000ReadyCheck(void);  
extern BOOL F_Dm9000InUseCheck(void);
extern BOOL F_Dm9000Allocate(INT16U UserId);
extern BOOL F_Dm9000Release(INT16U UserId);  
extern BOOL F_Dm9000InitialStart(INT16U UserId);
extern void F_Dm9000Reset(void);    
extern BOOL F_Dm9000Probe(void);
extern void F_Dm9000ModeSet(INT8U Mode);
extern BOOL F_Dm9000MacAddressSet(INT16U UserId,INT8U *pMacAddress);
extern BOOL F_Dm9000IpAddressSet(INT16U UserId,INT8U *pIpAddress);
extern INT8U F_Dm9000InitialPassCheck(void);
extern BOOL F_Dm9000PacketTransmit(INT8U *pPacketData,INT16U PacketLength);
extern INT32U F_Dm9000PacketReceive(INT8U *pPacketData,INT32U PacketLength);
extern BOOL F_Dm9000PacketReceiveCheck(void);
extern INT8U F_Dm9000IoRead(INT8U Address);    
extern void F_Dm9000IoWrite(INT8U Address,INT8U Data);
extern INT16U F_Dm9000PhyRead(INT8U RegisterAddr);
extern void F_Dm9000PhyWrite(INT8U RegisterAddr,INT16U Value);

#endif