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dma0.c
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1 /******************************************************
2 * Function: s3c2440 dma0 driver
3 *
4 * File: dma0.c
5 * Author: Book Chen
6 * Date: 2008.07.18
7 *******************************************************
8 */
9 #include "includes.h"
10 
11 #define Dma0IdleState 0
12 
14 
15 void F_Dma0Init(void);
16 void F_Dma0Svc(void);
19 INT8U F_Dma0Release(INT16U UserId);
20 INT8U F_Dma0Reset(INT16U UserId);
21 INT8U F_Dma0Request(INT16U UserId);
22 INT8U F_Dma0Start(INT16U UserId);
23 INT8U F_Dma0Stop(INT16U UserId);
24 INT8U F_Dma0Run(INT16U UserId);
25 INT8U F_Dma0DisrcSet(INT16U UserId,INT32U InitialSource);
26 INT8U F_Dma0DidstSet(INT16U UserId,INT32U InitialDestination);
27 INT8U F_Dma0DisrccSet(INT16U UserId,INT32U InitialSourceCtrl);
28 INT8U F_Dma0DidstcSet(INT16U UserId,INT32U InitialDestinationCtrl);
29 INT8U F_Dma0DconSet(INT16U UserId,INT32U DmaControl);
30 INT8U F_Dma0LengthSet(INT16U UserId,INT32U Length);
31 INT8U F_Dma0TriggerModeSet(INT16U UserId,INT8U TriggerMode);
34 INT8U F_Dma0DisrcSetIsr(INT16U UserId,INT32U InitialSource);
35 INT8U F_Dma0DidstSetIsr(INT16U UserId,INT32U InitialDestination);
36 INT8U F_Dma0LengthSetIsr(INT16U UserId,INT32U Length);
38 
39 void F_Dma0Init(void){
40  // initial hw sfr
41  Dma0Ctrl.pDma0Register=(DMA0_REGISTER *)(0x4b000000);
42  //Dma0Ctrl.pDma0Register->DISRC=(DMA0_REGISTER *)(0x4b000000);
43  //Dma0Ctrl.pDma0Register->DMASKTRIG=0x04; // stop dma
44  Dma0Ctrl.pDma0Register->DISRCC=0; // sourc in ahb, increment
45  Dma0Ctrl.pDma0Register->DIDSTC=0; // destination in ahb, increment
46  Dma0Ctrl.pDma0Register->DCON=0; // HWSRCSEL is I2SSDO
47  // variable initial
48  Dma0Ctrl.Id=ID_DMA0;
49  Dma0Ctrl.InUse=FALSE;
50  Dma0Ctrl.Status=0;
51  Dma0Ctrl.State=Dma0IdleState;
52 }
53 void F_Dma0Svc(void){}
55  if(Dma0Ctrl.State==Dma0IdleState) return TRUE;
56  else return FALSE;
57 }
59  if(Dma0Ctrl.InUse==TRUE) return TRUE; // resource is in use
60  else return FALSE; // resource is not in use
61 }
63  if(Dma0Ctrl.InUse==TRUE) return FALSE;
64  else{
65  Dma0Ctrl.InUse=TRUE;
66  Dma0Ctrl.UserId=UserId;
67  return TRUE; // resource is allocated
68  }
69 }
71  if(Dma0Ctrl.InUse==TRUE){
72  if(Dma0Ctrl.UserId==UserId){
73  Dma0Ctrl.pDma0Register->DMASKTRIG=0; // dma stop,channel off
74  Dma0Ctrl.InUse=FALSE;
75  return TRUE; // resource is relased
76  }
77  else return FALSE; // resource is not relased...invalid user id
78  }
79  else return TRUE; // resource is relased before
80 }
82  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
83  Dma0Ctrl.State=Dma0IdleState;
84  return TRUE;
85  }
86  else return FALSE;
87 }
88 /*INT8U F_Dma0RequestSourceSet(INT16U UserId,INT8U RequestSource){
89  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
90  if(RequestSource>4) return FALSE; // source= 0,1,2,3,4
91  Dma0Ctrl.RequestSource=RequestSource;
92  return TRUE;
93  }
94  else return FALSE;
95 }*/
96 INT8U F_Dma0DisrcSet(INT16U UserId,INT32U InitialSource){
97  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
98  Dma0Ctrl.pDma0Register->DISRC=InitialSource;
99  return TRUE;
100  }
101  else return FALSE;
102 }
103 INT8U F_Dma0DidstSet(INT16U UserId,INT32U InitialDestination){
104  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
105  Dma0Ctrl.pDma0Register->DIDST=InitialDestination;
106  return TRUE;
107  }
108  else return FALSE;
109 }
110 INT8U F_Dma0DisrccSet(INT16U UserId,INT32U InitialSourceCtrl){
111  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
112  Dma0Ctrl.pDma0Register->DISRCC=InitialSourceCtrl;
113  return TRUE;
114  }
115  else return FALSE;
116 }
117 INT8U F_Dma0DidstcSet(INT16U UserId,INT32U InitialDestinationCtrl){
118  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
119  Dma0Ctrl.pDma0Register->DIDSTC=InitialDestinationCtrl;
120  return TRUE;
121  }
122  else return FALSE;
123 }
124 INT8U F_Dma0DconSet(INT16U UserId,INT32U DmaControl){
125  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
126  Dma0Ctrl.pDma0Register->DCON=DmaControl;
127  return TRUE;
128  }
129  else return FALSE;
130 }
132  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
133  Dma0Ctrl.pDma0Register->DCON&=~0xfffff;
134  Dma0Ctrl.pDma0Register->DCON|=Length&0xfffff;
135  return TRUE;
136  }
137  else return FALSE;
138 }
140  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
141  if(TriggerMode==DMA0_TRIGGER_HW)
142  Dma0Ctrl.TriggerMode=DMA0_TRIGGER_HW; // hardware trigger
143  else if(TriggerMode==DMA0_TRIGGER_SW)
144  Dma0Ctrl.TriggerMode=DMA0_TRIGGER_SW; // software trigger
145  else
146  Dma0Ctrl.TriggerMode=DMA0_TRIGGER_SW; // software trigger
147  return TRUE;
148  }
149  else return FALSE;
150 }
152  return TRUE;
153 }
155  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
156  if(Dma0Ctrl.TriggerMode==DMA0_TRIGGER_HW)
157  Dma0Ctrl.pDma0Register->DMASKTRIG=2; // channel on
158  else
159  Dma0Ctrl.pDma0Register->DMASKTRIG=3; // channel on & software trigger
160  return TRUE;
161  }
162  else return FALSE;
163 }
165  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
166  Dma0Ctrl.pDma0Register->DMASKTRIG=1<<2; // stop the DMA operation
167  return TRUE;
168  }
169  else return FALSE;
170 }
172  return FALSE;
173 }
175  // DSTAT[21:20]==00 DMA ready for another transfer
176  // DSTAT[21:20]==01 DMA busy
177  // DSTAT[19: 0] transfer counter...CURR_TC-- to 0
178  return Dma0Ctrl.pDma0Register->DSTAT;
179 }
181  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
182  pISR_DMA0=Function;
183  return TRUE;
184  }
185  else return FALSE;
186 }
187 INT8U F_Dma0DisrcSetIsr(INT16U UserId,INT32U InitialSource){
188  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
189  Dma0Ctrl.pDma0Register->DISRCC=InitialSource;
190  return TRUE;
191  }
192  else return FALSE;
193 }
194 INT8U F_Dma0DidstSetIsr(INT16U UserId,INT32U InitialDestination){
195  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
196  Dma0Ctrl.pDma0Register->DIDST=InitialDestination;
197  return TRUE;
198  }
199  else return FALSE;
200 }
202  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
203  Dma0Ctrl.pDma0Register->DCON&=~0xfffff;
204  Dma0Ctrl.pDma0Register->DCON|=Length&0xfffff;
205  return TRUE;
206  }
207  else return FALSE;
208 }
210  if((Dma0Ctrl.InUse==TRUE)&&(Dma0Ctrl.UserId==UserId)){
211  if(Dma0Ctrl.TriggerMode==DMA0_TRIGGER_HW)
212  Dma0Ctrl.pDma0Register->DMASKTRIG=2; // channel on
213  else
214  Dma0Ctrl.pDma0Register->DMASKTRIG=3; // channel on & software trigger
215  return TRUE;
216  }
217  else return FALSE;
218 }
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