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dma1.c
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1 /******************************************************
2 * Function: s3c2440 dma1 driver
3 *
4 * File: dma1.c
5 * Author: Book Chen
6 * Date: 2008.07.18
7 *******************************************************
8 */
9 #include "includes.h"
10 
11 #define Dma1IdleState 0
12 
14 
15 void F_Dma1Init(void);
16 void F_Dma1Svc(void);
19 INT8U F_Dma1Release(INT16U UserId);
20 INT8U F_Dma1Reset(INT16U UserId);
21 INT8U F_Dma1Request(INT16U UserId);
22 INT8U F_Dma1Start(INT16U UserId);
23 INT8U F_Dma1Stop(INT16U UserId);
24 INT8U F_Dma1Run(INT16U UserId);
25 INT8U F_Dma1DisrcSet(INT16U UserId,INT32U InitialSource);
26 INT8U F_Dma1DidstSet(INT16U UserId,INT32U InitialDestination);
27 INT8U F_Dma1DisrccSet(INT16U UserId,INT32U InitialSourceCtrl);
28 INT8U F_Dma1DidstcSet(INT16U UserId,INT32U InitialDestinationCtrl);
29 INT8U F_Dma1DconSet(INT16U UserId,INT32U DmaControl);
30 INT8U F_Dma1LengthSet(INT16U UserId,INT32U Length);
31 INT8U F_Dma1TriggerModeSet(INT16U UserId,INT8U TriggerMode);
34 INT8U F_Dma1DisrcSetIsr(INT16U UserId,INT32U InitialSource);
35 INT8U F_Dma1DidstSetIsr(INT16U UserId,INT32U InitialDestination);
36 INT8U F_Dma1LengthSetIsr(INT16U UserId,INT32U Length);
38 
39 
40 void F_Dma1Init(void){
41  // initial hw sfr
42  Dma1Ctrl.pDma1Register=(DMA1_REGISTER *)(0x4b000040);
43  //Dma1Ctrl.pDma1Register->DISRC=(DMA1_REGISTER *)(0x4b000040);
44  Dma1Ctrl.pDma1Register->DMASKTRIG=0x04; // stop dma
45  Dma1Ctrl.pDma1Register->DISRCC=0; // sourc in ahb, increment
46  Dma1Ctrl.pDma1Register->DIDSTC=0; // destination in ahb, increment
47  Dma1Ctrl.pDma1Register->DCON=0; // HWSRCSEL is I2SSDO
48  // variable initial
49  Dma1Ctrl.Id=ID_DMA1;
50  Dma1Ctrl.InUse=FALSE;
51  Dma1Ctrl.Status=0;
52  Dma1Ctrl.State=Dma1IdleState;
53 }
54 void F_Dma1Svc(void){}
56  if(Dma1Ctrl.State==Dma1IdleState) return TRUE;
57  else return FALSE;
58 }
60  if(Dma1Ctrl.InUse==TRUE) return TRUE; // resource is in use
61  else return FALSE; // resource is not in use
62 }
64  if(Dma1Ctrl.InUse==TRUE) return FALSE;
65  else{
66  Dma1Ctrl.InUse=TRUE;
67  Dma1Ctrl.UserId=UserId;
68  return TRUE; // resource is allocated
69  }
70 }
72  if(Dma1Ctrl.InUse==TRUE){
73  if(Dma1Ctrl.UserId==UserId){
74  Dma1Ctrl.pDma1Register->DMASKTRIG=0; // dma stop,channel off
75  Dma1Ctrl.InUse=FALSE;
76  return TRUE; // resource is relased
77  }
78  else return FALSE; // resource is not relased...invalid user id
79  }
80  else return TRUE; // resource is relased before
81 }
83  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
84  Dma1Ctrl.State=Dma1IdleState;
85  return TRUE;
86  }
87  else return FALSE;
88 }
89 /*INT8U F_Dma1RequestSourceSet(INT16U UserId,INT8U RequestSource){
90  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
91  if(RequestSource>4) return FALSE; // source= 0,1,2,3,4
92  Dma1Ctrl.RequestSource=RequestSource;
93  return TRUE;
94  }
95  else return FALSE;
96 }*/
97 INT8U F_Dma1DisrcSet(INT16U UserId,INT32U InitialSource){
98  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
99  Dma1Ctrl.pDma1Register->DISRC=InitialSource;
100  return TRUE;
101  }
102  else return FALSE;
103 }
104 INT8U F_Dma1DidstSet(INT16U UserId,INT32U InitialDestination){
105  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
106  Dma1Ctrl.pDma1Register->DIDST=InitialDestination;
107  return TRUE;
108  }
109  else return FALSE;
110 }
111 INT8U F_Dma1DisrccSet(INT16U UserId,INT32U InitialSourceCtrl){
112  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
113  Dma1Ctrl.pDma1Register->DISRCC=InitialSourceCtrl;
114  return TRUE;
115  }
116  else return FALSE;
117 }
118 INT8U F_Dma1DidstcSet(INT16U UserId,INT32U InitialDestinationCtrl){
119  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
120  Dma1Ctrl.pDma1Register->DIDSTC=InitialDestinationCtrl;
121  return TRUE;
122  }
123  else return FALSE;
124 }
125 INT8U F_Dma1DconSet(INT16U UserId,INT32U DmaControl){
126  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
127  Dma1Ctrl.pDma1Register->DCON=DmaControl;
128  return TRUE;
129  }
130  else return FALSE;
131 }
133  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
134  Dma1Ctrl.pDma1Register->DCON&=~0xfffff;
135  Dma1Ctrl.pDma1Register->DCON|=Length&0xfffff;
136  return TRUE;
137  }
138  else return FALSE;
139 }
141  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
142  if(TriggerMode==DMA1_TRIGGER_HW)
143  Dma1Ctrl.TriggerMode=DMA1_TRIGGER_HW; // hardware trigger
144  else if(TriggerMode==DMA1_TRIGGER_SW)
145  Dma1Ctrl.TriggerMode=DMA1_TRIGGER_SW; // software trigger
146  else
147  Dma1Ctrl.TriggerMode=DMA1_TRIGGER_SW; // software trigger
148  return TRUE;
149  }
150  else return FALSE;
151 }
153  return TRUE;
154 }
156  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
157  if(Dma1Ctrl.TriggerMode==DMA1_TRIGGER_HW)
158  Dma1Ctrl.pDma1Register->DMASKTRIG=2; // channel on
159  else
160  Dma1Ctrl.pDma1Register->DMASKTRIG=3; // channel on & software trigger
161  return TRUE;
162  }
163  else return FALSE;
164 }
166  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
167  Dma1Ctrl.pDma1Register->DMASKTRIG=1<<2; // stop the DMA operation
168  return TRUE;
169  }
170  else return FALSE;
171 }
173  return FALSE;
174 }
176  // DSTAT[21:20]==00 DMA ready for another transfer
177  // DSTAT[21:20]==01 DMA busy
178  // DSTAT[19: 0] transfer counter...CURR_TC-- to 0
179  return Dma1Ctrl.pDma1Register->DSTAT;
180 }
182  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
183  pISR_DMA1=Function;
184  return TRUE;
185  }
186  else return FALSE;
187 }
188 INT8U F_Dma1DisrcSetIsr(INT16U UserId,INT32U InitialSource){
189  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
190  Dma1Ctrl.pDma1Register->DISRCC=InitialSource;
191  return TRUE;
192  }
193  else return FALSE;
194 }
195 INT8U F_Dma1DidstSetIsr(INT16U UserId,INT32U InitialDestination){
196  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
197  Dma1Ctrl.pDma1Register->DIDST=InitialDestination;
198  return TRUE;
199  }
200  else return FALSE;
201 }
203  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
204  Dma1Ctrl.pDma1Register->DCON&=~0xfffff;
205  Dma1Ctrl.pDma1Register->DCON|=Length&0xfffff;
206  return TRUE;
207  }
208  else return FALSE;
209 }
211  if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
212  if(Dma1Ctrl.TriggerMode==DMA1_TRIGGER_HW)
213  Dma1Ctrl.pDma1Register->DMASKTRIG=2; // channel on
214  else
215  Dma1Ctrl.pDma1Register->DMASKTRIG=3; // channel on & software trigger
216  return TRUE;
217  }
218  else return FALSE;
219 }