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bootloader
drivers
dma1.c
Go to the documentation of this file.
1
/******************************************************
2
* Function: s3c2440 dma1 driver
3
*
4
* File: dma1.c
5
* Author: Book Chen
6
* Date: 2008.07.18
7
*******************************************************
8
*/
9
#include "
includes.h
"
10
11
#define Dma1IdleState 0
12
13
DMA1_CONTROL
Dma1Ctrl
;
14
15
void
F_Dma1Init
(
void
);
16
void
F_Dma1Svc
(
void
);
17
INT8U
F_Dma1InUseCheck
(
void
);
18
INT8U
F_Dma1Allocate
(
INT16U
UserId);
19
INT8U
F_Dma1Release
(
INT16U
UserId);
20
INT8U
F_Dma1Reset
(
INT16U
UserId);
21
INT8U
F_Dma1Request
(
INT16U
UserId);
22
INT8U
F_Dma1Start
(
INT16U
UserId);
23
INT8U
F_Dma1Stop
(
INT16U
UserId);
24
INT8U
F_Dma1Run
(
INT16U
UserId);
25
INT8U
F_Dma1DisrcSet
(
INT16U
UserId,
INT32U
InitialSource);
26
INT8U
F_Dma1DidstSet
(
INT16U
UserId,
INT32U
InitialDestination);
27
INT8U
F_Dma1DisrccSet
(
INT16U
UserId,
INT32U
InitialSourceCtrl);
28
INT8U
F_Dma1DidstcSet
(
INT16U
UserId,
INT32U
InitialDestinationCtrl);
29
INT8U
F_Dma1DconSet
(
INT16U
UserId,
INT32U
DmaControl);
30
INT8U
F_Dma1LengthSet
(
INT16U
UserId,
INT32U
Length);
31
INT8U
F_Dma1TriggerModeSet
(
INT16U
UserId,
INT8U
TriggerMode);
32
INT32U
F_Dma1StatusRegisterGet
(
void
);
33
INT8U
F_Dma1IsrHookFunctionSet
(
INT16U
UserId,
INT32U
Function);
34
INT8U
F_Dma1DisrcSetIsr
(
INT16U
UserId,
INT32U
InitialSource);
35
INT8U
F_Dma1DidstSetIsr
(
INT16U
UserId,
INT32U
InitialDestination);
36
INT8U
F_Dma1LengthSetIsr
(
INT16U
UserId,
INT32U
Length);
37
INT8U
F_Dma1StartIsr
(
INT16U
UserId);
38
39
40
void
F_Dma1Init
(
void
){
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// initial hw sfr
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Dma1Ctrl.
pDma1Register
=(
DMA1_REGISTER
*)(0x4b000040);
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//Dma1Ctrl.pDma1Register->DISRC=(DMA1_REGISTER *)(0x4b000040);
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Dma1Ctrl.
pDma1Register
->
DMASKTRIG
=0x04;
// stop dma
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Dma1Ctrl.
pDma1Register
->
DISRCC
=0;
// sourc in ahb, increment
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Dma1Ctrl.
pDma1Register
->
DIDSTC
=0;
// destination in ahb, increment
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Dma1Ctrl.
pDma1Register
->
DCON
=0;
// HWSRCSEL is I2SSDO
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// variable initial
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Dma1Ctrl.
Id
=
ID_DMA1
;
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Dma1Ctrl.
InUse
=
FALSE
;
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Dma1Ctrl.
Status
=0;
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Dma1Ctrl.
State
=
Dma1IdleState
;
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}
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void
F_Dma1Svc
(
void
){}
55
INT8U
F_Dma1StatusCheck
(
void
){
56
if
(Dma1Ctrl.
State
==
Dma1IdleState
)
return
TRUE
;
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else
return
FALSE
;
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}
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INT8U
F_Dma1InUseCheck
(
void
){
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if
(Dma1Ctrl.
InUse
==
TRUE
)
return
TRUE
;
// resource is in use
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else
return
FALSE
;
// resource is not in use
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}
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INT8U
F_Dma1Allocate
(
INT16U
UserId){
64
if
(Dma1Ctrl.
InUse
==
TRUE
)
return
FALSE
;
65
else
{
66
Dma1Ctrl.
InUse
=
TRUE
;
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Dma1Ctrl.
UserId
=UserId;
68
return
TRUE
;
// resource is allocated
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}
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}
71
INT8U
F_Dma1Release
(
INT16U
UserId){
72
if
(Dma1Ctrl.
InUse
==
TRUE
){
73
if
(Dma1Ctrl.
UserId
==UserId){
74
Dma1Ctrl.
pDma1Register
->
DMASKTRIG
=0;
// dma stop,channel off
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Dma1Ctrl.
InUse
=
FALSE
;
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return
TRUE
;
// resource is relased
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}
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else
return
FALSE
;
// resource is not relased...invalid user id
79
}
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else
return
TRUE
;
// resource is relased before
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}
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INT8U
F_Dma1Reset
(
INT16U
UserId){
83
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
84
Dma1Ctrl.
State
=
Dma1IdleState
;
85
return
TRUE
;
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}
87
else
return
FALSE
;
88
}
89
/*INT8U F_Dma1RequestSourceSet(INT16U UserId,INT8U RequestSource){
90
if((Dma1Ctrl.InUse==TRUE)&&(Dma1Ctrl.UserId==UserId)){
91
if(RequestSource>4) return FALSE; // source= 0,1,2,3,4
92
Dma1Ctrl.RequestSource=RequestSource;
93
return TRUE;
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}
95
else return FALSE;
96
}*/
97
INT8U
F_Dma1DisrcSet
(
INT16U
UserId,
INT32U
InitialSource){
98
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
99
Dma1Ctrl.
pDma1Register
->
DISRC
=InitialSource;
100
return
TRUE
;
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}
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else
return
FALSE
;
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}
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INT8U
F_Dma1DidstSet
(
INT16U
UserId,
INT32U
InitialDestination){
105
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
106
Dma1Ctrl.
pDma1Register
->
DIDST
=InitialDestination;
107
return
TRUE
;
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}
109
else
return
FALSE
;
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}
111
INT8U
F_Dma1DisrccSet
(
INT16U
UserId,
INT32U
InitialSourceCtrl){
112
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
113
Dma1Ctrl.
pDma1Register
->
DISRCC
=InitialSourceCtrl;
114
return
TRUE
;
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}
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else
return
FALSE
;
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}
118
INT8U
F_Dma1DidstcSet
(
INT16U
UserId,
INT32U
InitialDestinationCtrl){
119
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
120
Dma1Ctrl.
pDma1Register
->
DIDSTC
=InitialDestinationCtrl;
121
return
TRUE
;
122
}
123
else
return
FALSE
;
124
}
125
INT8U
F_Dma1DconSet
(
INT16U
UserId,
INT32U
DmaControl){
126
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
127
Dma1Ctrl.
pDma1Register
->
DCON
=DmaControl;
128
return
TRUE
;
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}
130
else
return
FALSE
;
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}
132
INT8U
F_Dma1LengthSet
(
INT16U
UserId,
INT32U
Length){
133
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
134
Dma1Ctrl.
pDma1Register
->
DCON
&=~0xfffff;
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Dma1Ctrl.
pDma1Register
->
DCON
|=Length&0xfffff;
136
return
TRUE
;
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}
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else
return
FALSE
;
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}
140
INT8U
F_Dma1TriggerModeSet
(
INT16U
UserId,
INT8U
TriggerMode){
141
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
142
if
(TriggerMode==
DMA1_TRIGGER_HW
)
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Dma1Ctrl.
TriggerMode
=
DMA1_TRIGGER_HW
;
// hardware trigger
144
else
if
(TriggerMode==
DMA1_TRIGGER_SW
)
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Dma1Ctrl.
TriggerMode
=
DMA1_TRIGGER_SW
;
// software trigger
146
else
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Dma1Ctrl.
TriggerMode
=
DMA1_TRIGGER_SW
;
// software trigger
148
return
TRUE
;
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}
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else
return
FALSE
;
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}
152
INT8U
F_Dma1Request
(
INT16U
UserId){
153
return
TRUE
;
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}
155
INT8U
F_Dma1Start
(
INT16U
UserId){
156
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
157
if
(Dma1Ctrl.
TriggerMode
==
DMA1_TRIGGER_HW
)
158
Dma1Ctrl.
pDma1Register
->
DMASKTRIG
=2;
// channel on
159
else
160
Dma1Ctrl.
pDma1Register
->
DMASKTRIG
=3;
// channel on & software trigger
161
return
TRUE
;
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}
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else
return
FALSE
;
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}
165
INT8U
F_Dma1Stop
(
INT16U
UserId){
166
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
167
Dma1Ctrl.
pDma1Register
->
DMASKTRIG
=1<<2;
// stop the DMA operation
168
return
TRUE
;
169
}
170
else
return
FALSE
;
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}
172
INT8U
F_Dma1Run
(
INT16U
UserId){
173
return
FALSE
;
174
}
175
INT32U
F_Dma1StatusRegisterGet
(
void
){
176
// DSTAT[21:20]==00 DMA ready for another transfer
177
// DSTAT[21:20]==01 DMA busy
178
// DSTAT[19: 0] transfer counter...CURR_TC-- to 0
179
return
Dma1Ctrl.
pDma1Register
->
DSTAT
;
180
}
181
INT8U
F_Dma1IsrHookFunctionSet
(
INT16U
UserId,
INT32U
Function){
182
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
183
pISR_DMA1
=Function;
184
return
TRUE
;
185
}
186
else
return
FALSE
;
187
}
188
INT8U
F_Dma1DisrcSetIsr
(
INT16U
UserId,
INT32U
InitialSource){
189
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
190
Dma1Ctrl.
pDma1Register
->
DISRCC
=InitialSource;
191
return
TRUE
;
192
}
193
else
return
FALSE
;
194
}
195
INT8U
F_Dma1DidstSetIsr
(
INT16U
UserId,
INT32U
InitialDestination){
196
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
197
Dma1Ctrl.
pDma1Register
->
DIDST
=InitialDestination;
198
return
TRUE
;
199
}
200
else
return
FALSE
;
201
}
202
INT8U
F_Dma1LengthSetIsr
(
INT16U
UserId,
INT32U
Length){
203
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
204
Dma1Ctrl.
pDma1Register
->
DCON
&=~0xfffff;
205
Dma1Ctrl.
pDma1Register
->
DCON
|=Length&0xfffff;
206
return
TRUE
;
207
}
208
else
return
FALSE
;
209
}
210
INT8U
F_Dma1StartIsr
(
INT16U
UserId){
211
if
((Dma1Ctrl.
InUse
==
TRUE
)&&(Dma1Ctrl.
UserId
==UserId)){
212
if
(Dma1Ctrl.
TriggerMode
==
DMA1_TRIGGER_HW
)
213
Dma1Ctrl.
pDma1Register
->
DMASKTRIG
=2;
// channel on
214
else
215
Dma1Ctrl.
pDma1Register
->
DMASKTRIG
=3;
// channel on & software trigger
216
return
TRUE
;
217
}
218
else
return
FALSE
;
219
}
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