dma1.h

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#ifndef DMA1_H
#define DMA1_H

#define DMA1_nXDREQ1  0
#define DMA1_UART1    1
#define DMA1_IISSDI   2
#define DMA1_SPI0     3
#define DMA1_USBD_EP2 4

#define DMA1_TRIGGER_HW 0
#define DMA1_TRIGGER_SW 1

// DISRCC, DIDSTC parameters
#define DMA1_SRC_LOC_APB        0x02
#define DMA1_SRC_LOC_AHB        0x00
#define DMA1_SRC_ADDR_FIXED     0x01
#define DMA1_SRC_ADDR_INC       0x00
#define DMA1_DST_LOC_APB        0x02
#define DMA1_DST_LOC_AHB        0x00
#define DMA1_DST_ADDR_FIXED     0x01
#define DMA1_DST_ADDR_INC       0x00    
// DCON paramaters
#define DMA1_HANDSHAKE_MODE     0x80000000      //[31]
#define DMA1_DEMAND_MODE        0x00000000
#define DMA1_SYNC_AHB           0x40000000      //[30]
#define DMA1_SYNC_APB           0x00000000
#define DMA1_DONE_GEN_INT       0x20000000      //[29]
#define DMA1_DONE_NO_INT        0x00000000
#define DMA1_TSZ_BURST          0x10000000      //[28]
#define DMA1_TSZ_UNIT           0x00000000
#define DMA1_WHOLE_SVC          0x08000000      //[27]
#define DMA1_SINGLE_SVC         0x00000000
#define DMA1_HW_TRIG            0x00800000      //[23]
#define DMA1_SW_TRIG            0x00000000
#define DMA1_RELOAD_OFF         0x00400000      //[22]
#define DMA1_RELOAD_ON          0x00000000
#define DMA1_DSZ_8b                     0x00000000
#define DMA1_DSZ_16b            0x00100000
#define DMA1_DSZ_32b            0x00200000      //[21:20]

typedef struct{                                         
    volatile U32 DISRC;     //0x0
    volatile U32 DISRCC;    //0x4
    volatile U32 DIDST;     //0x8
    volatile U32 DIDSTC;    //0xc
    volatile U32 DCON;      //0x10
    volatile U32 DSTAT;     //0x14
    volatile U32 DCSRC;     //0x18
    volatile U32 DCDST;     //0x1c
    volatile U32 DMASKTRIG; //0x20
}DMA1_REGISTER;

typedef struct{
    INT8U State;
    INT8U Status;
    INT8U InUse;
    INT8U RequestSource;
    INT8U TriggerMode;
    INT16U Id;
    INT16U UserId;
    INT32U SourceAddr;
    INT32U DestinationAddr;
    DMA1_REGISTER *pDma1Register;         
}DMA1_CONTROL;

extern DMA1_CONTROL Dma1Ctrl;

extern void F_Dma1Init(void);
extern void F_Dma1Svc(void);
extern INT8U F_Dma1InUseCheck(void);
extern INT8U F_Dma1Allocate(INT16U UserId);
extern INT8U F_Dma1Release(INT16U UserId);
extern INT8U F_Dma1Reset(INT16U UserId);
extern INT8U F_Dma1Request(INT16U UserId);
extern INT8U F_Dma1Start(INT16U UserId);
extern INT8U F_Dma1Stop(INT16U UserId);
extern INT8U F_Dma1Run(INT16U UserId);
extern INT8U F_Dma1DisrcSet(INT16U UserId,INT32U InitialSource);
extern INT8U F_Dma1DidstSet(INT16U UserId,INT32U InitialDestination);
extern INT8U F_Dma1DisrccSet(INT16U UserId,INT32U InitialSourceCtrl);
extern INT8U F_Dma1DidstcSet(INT16U UserId,INT32U InitialDestinationCtrl);
extern INT8U F_Dma1DconSet(INT16U UserId,INT32U DmaControl);
extern INT8U F_Dma1LengthSet(INT16U UserId,INT32U Length);
extern INT8U F_Dma1TriggerModeSet(INT16U UserId,INT8U TriggerMode);
extern INT32U F_Dma1StatusRegisterGet(void);
extern INT8U F_Dma1IsrHookFunctionSet(INT16U UserId,INT32U Function);
extern INT8U F_Dma1DisrcSetIsr(INT16U UserId,INT32U InitialSource);
extern INT8U F_Dma1DidstSetIsr(INT16U UserId,INT32U InitialDestination);
extern INT8U F_Dma1LengthSetIsr(INT16U UserId,INT32U Length);
extern INT8U F_Dma1StartIsr(INT16U UserId);

#endif