BOOTLOADER
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros
dma2.c
Go to the documentation of this file.
1 /******************************************************
2 * Function: s3c2440 dma2 driver
3 *
4 * File: dma2.c
5 * Author: Book Chen
6 * Date: 2008.07.18
7 *******************************************************
8 */
9 
10 #include "includes.h"
11 
12 #define Dma2IdleState 0
13 
15 
16 void F_Dma2Init(void);
17 void F_Dma2Svc(void);
20 INT8U F_Dma2Release(INT16U UserId);
21 INT8U F_Dma2Reset(INT16U UserId);
22 INT8U F_Dma2Request(INT16U UserId);
23 INT8U F_Dma2Start(INT16U UserId);
24 INT8U F_Dma2Stop(INT16U UserId);
25 INT8U F_Dma2Run(INT16U UserId);
26 INT8U F_Dma2DisrcSet(INT16U UserId,INT32U InitialSource);
27 INT8U F_Dma2DidstSet(INT16U UserId,INT32U InitialDestination);
28 INT8U F_Dma2DisrccSet(INT16U UserId,INT32U InitialSourceCtrl);
29 INT8U F_Dma2DidstcSet(INT16U UserId,INT32U InitialDestinationCtrl);
30 INT8U F_Dma2DconSet(INT16U UserId,INT32U DmaControl);
31 INT8U F_Dma2LengthSet(INT16U UserId,INT32U Length);
32 INT8U F_Dma2TriggerModeSet(INT16U UserId,INT8U TriggerMode);
35 INT8U F_Dma2DisrcSetIsr(INT16U UserId,INT32U InitialSource);
36 INT8U F_Dma2DidstSetIsr(INT16U UserId,INT32U InitialDestination);
37 INT8U F_Dma2LengthSetIsr(INT16U UserId,INT32U Length);
39 
40 void F_Dma2Init(void){
41  // initial hw sfr
42  Dma2Ctrl.pDma2Register=(DMA2_REGISTER *)(0x4b000080);
43  //Dma2Ctrl.pDma2Register->DISRC=(DMA2_REGISTER *)(0x4b000080);
44  //Dma2Ctrl.pDma2Register->DMASKTRIG=0x04; // stop dma
45  Dma2Ctrl.pDma2Register->DISRCC=0; // sourc in ahb, increment
46  Dma2Ctrl.pDma2Register->DIDSTC=0; // destination in ahb, increment
47  Dma2Ctrl.pDma2Register->DCON=0; // HWSRCSEL is I2SSDO
48  // variable initial
49  Dma2Ctrl.State=Dma2IdleState;
50  Dma2Ctrl.InUse=FALSE;
51  Dma2Ctrl.Status=0;
52  Dma2Ctrl.Id=ID_DMA2;
53 }
54 void F_Dma2Svc(void){}
56  if(Dma2Ctrl.State==Dma2IdleState) return TRUE;
57  else return FALSE;
58 }
60  if(Dma2Ctrl.InUse==TRUE) return TRUE; // resource is in use
61  else return FALSE; // resource is not in use
62 }
64  if(Dma2Ctrl.InUse==TRUE) return FALSE;
65  else{
66  Dma2Ctrl.InUse=TRUE;
67  Dma2Ctrl.UserId=UserId;
68  return TRUE; // resource is allocated
69  }
70 }
72  if(Dma2Ctrl.InUse==TRUE){
73  if(Dma2Ctrl.UserId==UserId){
74  Dma2Ctrl.pDma2Register->DMASKTRIG=0; // dma stop,channel off
75  Dma2Ctrl.InUse=FALSE;
76  return TRUE; // resource is relased
77  }
78  else return FALSE; // resource is not relased...invalid user id
79  }
80  else return TRUE; // resource is relased before
81 }
83  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
84  Dma2Ctrl.State=Dma2IdleState;
85  return TRUE;
86  }
87  else return FALSE;
88 }
89 /*INT8U F_Dma2RequestSourceSet(INT16U UserId,INT8U RequestSource){
90  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
91  if(RequestSource>4) return FALSE; // source= 0,1,2,3,4
92  Dma2Ctrl.RequestSource=RequestSource;
93  return TRUE;
94  }
95  else return FALSE;
96 }*/
97 INT8U F_Dma2DisrcSet(INT16U UserId,INT32U InitialSource){
98  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
99  Dma2Ctrl.pDma2Register->DISRC=InitialSource;
100  return TRUE;
101  }
102  else return FALSE;
103 }
104 INT8U F_Dma2DidstSet(INT16U UserId,INT32U InitialDestination){
105  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
106  Dma2Ctrl.pDma2Register->DIDST=InitialDestination;
107  return TRUE;
108  }
109  else return FALSE;
110 }
111 INT8U F_Dma2DisrccSet(INT16U UserId,INT32U InitialSourceCtrl){
112  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
113  Dma2Ctrl.pDma2Register->DISRCC=InitialSourceCtrl;
114  return TRUE;
115  }
116  else return FALSE;
117 }
118 INT8U F_Dma2DidstcSet(INT16U UserId,INT32U InitialDestinationCtrl){
119  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
120  Dma2Ctrl.pDma2Register->DIDSTC=InitialDestinationCtrl;
121  return TRUE;
122  }
123  else return FALSE;
124 }
125 INT8U F_Dma2DconSet(INT16U UserId,INT32U DmaControl){
126  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
127  Dma2Ctrl.pDma2Register->DCON=DmaControl;
128  return TRUE;
129  }
130  else return FALSE;
131 }
133  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
134  Dma2Ctrl.pDma2Register->DCON&=~0xfffff;
135  Dma2Ctrl.pDma2Register->DCON|=Length&0xfffff;
136  return TRUE;
137  }
138  else return FALSE;
139 }
141  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
142  if(TriggerMode==DMA2_TRIGGER_HW)
143  Dma2Ctrl.TriggerMode=DMA2_TRIGGER_HW; // hardware trigger
144  else if(TriggerMode==DMA2_TRIGGER_SW)
145  Dma2Ctrl.TriggerMode=DMA2_TRIGGER_SW; // software trigger
146  else
147  Dma2Ctrl.TriggerMode=DMA2_TRIGGER_HW; // software trigger
148  return TRUE;
149  }
150  else return FALSE;
151 }
153  return TRUE;
154 }
156  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
157  if(Dma2Ctrl.TriggerMode==DMA2_TRIGGER_HW)
158  Dma2Ctrl.pDma2Register->DMASKTRIG=2; // channel on
159  else
160  Dma2Ctrl.pDma2Register->DMASKTRIG=3; // channel on & software trigger
161  return TRUE;
162  }
163  else return FALSE;
164 }
166  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
167  Dma2Ctrl.pDma2Register->DMASKTRIG=1<<2; // stop the DMA operation
168  return TRUE;
169  }
170  else return FALSE;
171 }
173  return FALSE;
174 }
176  // DSTAT[21:20]==00 DMA ready for another transfer
177  // DSTAT[21:20]==01 DMA busy
178  // DSTAT[19: 0] transfer counter...CURR_TC-- to 0
179  return Dma2Ctrl.pDma2Register->DSTAT;
180 }
182  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
183  pISR_DMA2=Function;
184  return TRUE;
185  }
186  else return FALSE;
187 }
188 INT8U F_Dma2DisrcSetIsr(INT16U UserId,INT32U InitialSource){
189  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
190  Dma2Ctrl.pDma2Register->DISRCC=InitialSource;
191  return TRUE;
192  }
193  else return FALSE;
194 }
195 INT8U F_Dma2DidstSetIsr(INT16U UserId,INT32U InitialDestination){
196  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
197  Dma2Ctrl.pDma2Register->DIDST=InitialDestination;
198  return TRUE;
199  }
200  else return FALSE;
201 }
203  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
204  Dma2Ctrl.pDma2Register->DCON&=~0xfffff;
205  Dma2Ctrl.pDma2Register->DCON|=Length&0xfffff;
206  return TRUE;
207  }
208  else return FALSE;
209 }
211  if((Dma2Ctrl.InUse==TRUE)&&(Dma2Ctrl.UserId==UserId)){
212  if(Dma2Ctrl.TriggerMode==DMA2_TRIGGER_HW)
213  Dma2Ctrl.pDma2Register->DMASKTRIG=2; // channel on
214  else
215  Dma2Ctrl.pDma2Register->DMASKTRIG=3; // channel on & software trigger
216  return TRUE;
217  }
218  else return FALSE;
219 }