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dma3.h
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1 #ifndef DMA3_H
2 #define DMA3_H
3 
4 #define DMA3_UART2 0
5 #define DMA3_SDI 1
6 #define DMA3_SPI1 2
7 #define DMA3_TIMER 3
8 #define DMA3_USB_EP4 4
9 
10 #define DMA3_TRIGGER_HW 0
11 #define DMA3_TRIGGER_SW 1
12 
13 // DISRCC, DIDSTC parameters
14 #define DMA3_SRC_LOC_APB 0x02
15 #define DMA3_SRC_LOC_AHB 0x00
16 #define DMA3_SRC_ADDR_FIXED 0x01
17 #define DMA3_SRC_ADDR_INC 0x00
18 #define DMA3_DST_LOC_APB 0x02
19 #define DMA3_DST_LOC_AHB 0x00
20 #define DMA3_DST_ADDR_FIXED 0x01
21 #define DMA3_DST_ADDR_INC 0x00
22 // DCON paramaters
23 #define DMA3_HANDSHAKE_MODE 0x80000000 //[31]
24 #define DMA3_DEMAND_MODE 0x00000000
25 #define DMA3_SYNC_AHB 0x40000000 //[30]
26 #define DMA3_SYNC_APB 0x00000000
27 #define DMA3_DONE_GEN_INT 0x20000000 //[29]
28 #define DMA3_DONE_NO_INT 0x00000000
29 #define DMA3_TSZ_BURST 0x10000000 //[28]
30 #define DMA3_TSZ_UNIT 0x00000000
31 #define DMA3_WHOLE_SVC 0x08000000 //[27]
32 #define DMA3_SINGLE_SVC 0x00000000
33 #define DMA3_HW_TRIG 0x00800000 //[23]
34 #define DMA3_SW_TRIG 0x00000000
35 #define DMA3_RELOAD_OFF 0x00400000 //[22]
36 #define DMA3_RELOAD_ON 0x00000000
37 #define DMA3_DSZ_8b 0x00000000
38 #define DMA3_DSZ_16b 0x00100000
39 #define DMA3_DSZ_32b 0x00200000 //[21:20]
40 
41 typedef struct{
42  volatile U32 DISRC; //0x0
43  volatile U32 DISRCC; //0x4
44  volatile U32 DIDST; //0x8
45  volatile U32 DIDSTC; //0xc
46  volatile U32 DCON; //0x10
47  volatile U32 DSTAT; //0x14
48  volatile U32 DCSRC; //0x18
49  volatile U32 DCDST; //0x1c
50  volatile U32 DMASKTRIG; //0x20
51 }DMA3_REGISTER;
52 
53 typedef struct{
54  INT8U State;
55  INT8U Status;
56  INT8U InUse;
57  INT8U RequestSource;
58  INT8U TriggerMode;
59  INT16U Id;
60  INT16U UserId;
61  INT32U SourceAddr;
62  INT32U DestinationAddr;
63  DMA3_REGISTER *pDma3Register;
64 }DMA3_CONTROL;
65 
66 extern DMA3_CONTROL Dma3Ctrl;
67 
68 extern void F_Dma3Init(void);
69 extern void F_Dma3Svc(void);
70 extern INT8U F_Dma3InUseCheck(void);
71 extern INT8U F_Dma3Allocate(INT16U UserId);
72 extern INT8U F_Dma3Release(INT16U UserId);
73 extern INT8U F_Dma3Reset(INT16U UserId);
74 extern INT8U F_Dma3Request(INT16U UserId);
75 extern INT8U F_Dma3Start(INT16U UserId);
76 extern INT8U F_Dma3Stop(INT16U UserId);
77 extern INT8U F_Dma3Run(INT16U UserId);
78 extern INT8U F_Dma3DisrcSet(INT16U UserId,INT32U InitialSource);
79 extern INT8U F_Dma3DidstSet(INT16U UserId,INT32U InitialDestination);
80 extern INT8U F_Dma3DisrccSet(INT16U UserId,INT32U InitialSourceCtrl);
81 extern INT8U F_Dma3DidstcSet(INT16U UserId,INT32U InitialDestinationCtrl);
82 extern INT8U F_Dma3DconSet(INT16U UserId,INT32U DmaControl);
83 extern INT8U F_Dma3LengthSet(INT16U UserId,INT32U Length);
84 extern INT8U F_Dma3TriggerModeSet(INT16U UserId,INT8U TriggerMode);
85 extern INT32U F_Dma3StatusRegisterGet(void);
86 extern INT8U F_Dma3IsrHookFunctionSet(INT16U UserId,INT32U Function);
87 extern INT8U F_Dma3DisrcSetIsr(INT16U UserId,INT32U InitialSource);
88 extern INT8U F_Dma3DidstSetIsr(INT16U UserId,INT32U InitialDestination);
89 extern INT8U F_Dma3LengthSetIsr(INT16U UserId,INT32U Length);
90 extern INT8U F_Dma3StartIsr(INT16U UserId);
91 
92 #endif
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