BOOTLOADER
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros
testdma.c
Go to the documentation of this file.
1 /******************************************************
2 * Function: Test s3c2440 dma function
3 *
4 * File: testdma.c
5 * Author: Book Chen
6 * Date: 2008.07.18
7 *******************************************************
8 */
9 #include "includes.h"
10 
11 #define TestDmaIdleState 0
12 #define TestDmaDma0State0 1
13 #define TestDmaDma0State1 2
14 #define TestDmaDma1State0 3
15 #define TestDmaDma1State1 4
16 #define TestDmaDma2State0 5
17 #define TestDmaDma2State1 6
18 #define TestDmaDma3State0 7
19 #define TestDmaDma3State1 8
20 
21 //#define TEST_DMA_SOURCE_ADDR 0x31000000
22 //#define TEST_DMA_DESTINATION_ADR 0x31080000
23 //#define TEST_DMA_DATA_LENGTH 0x1000
24 #define TEST_DMA_SOURCE_ADDR 0x33500000
25 #define TEST_DMA_DESTINATION_ADR 0x33580000
26 #define TEST_DMA_DATA_LENGTH 0x1000
27 
28 TESTDMA_CONTROL TestDmaCtrl;
29 void F_TestDmaInit(void);
30 void F_TestDmaSvc(void);
31 INT8U F_TestDmaStatusCheck(void);
32 INT8U F_TestDmaStart(INT8U DmaNumber);
33 void __irq TestDmaDma0Isr(void);
34 void __irq TestDmaDma1Isr(void);
35 void __irq TestDmaDma2Isr(void);
36 void __irq TestDmaDma3Isr(void);
37 
38 void F_TestDmaInit(void){
39  TestDmaCtrl.Id=ID_TESTDMA;
40  TestDmaCtrl.TestMode=TEST_DMA_UNIT_8BIT;
41  TestDmaCtrl.InTransfer=FALSE;
42  TestDmaCtrl.State=TestDmaIdleState;
43 }
44 void F_TestDmaSvc(void){
45  INT32U DconValue;
46  INT32U ByteMode;
47 
48  switch(TestDmaCtrl.State){
49  case TestDmaIdleState:
50  break;
51  case TestDmaDma0State0:
52  if(F_Dma0InUseCheck()==TRUE) return;
53  if(TestDmaCtrl.TestMode==TEST_DMA_UNIT_8BIT){
54  printf("\n TEST_DMA_UNIT_8BIT");
55  ByteMode=1;
56  DconValue=(DMA0_HANDSHAKE_MODE|DMA0_SYNC_AHB|DMA0_DONE_GEN_INT|
57  DMA0_TSZ_UNIT|DMA0_WHOLE_SVC|DMA0_SW_TRIG|
58  DMA0_RELOAD_OFF|DMA0_DSZ_8b);
59  }
60  else if(TestDmaCtrl.TestMode==TEST_DMA_UNIT_16BIT){
61  printf("\n TEST_DMA_UNIT_16BIT");
62  ByteMode=2;
63  DconValue=(DMA0_HANDSHAKE_MODE|DMA0_SYNC_AHB|DMA0_DONE_GEN_INT|
64  DMA0_TSZ_UNIT|DMA0_WHOLE_SVC|DMA0_SW_TRIG|
65  DMA0_RELOAD_OFF|DMA0_DSZ_16b);
66  }
67  else if(TestDmaCtrl.TestMode==TEST_DMA_UNIT_32BIT){
68  printf("\n TEST_DMA_UNIT_32BIT");
69  ByteMode=4;
70  DconValue=(DMA0_HANDSHAKE_MODE|DMA0_SYNC_AHB|DMA0_DONE_GEN_INT|
71  DMA0_TSZ_UNIT|DMA0_WHOLE_SVC|DMA0_SW_TRIG|
72  DMA0_RELOAD_OFF|DMA0_DSZ_32b);
73  }
74  else if(TestDmaCtrl.TestMode==TEST_DMA_BURST_8BIT){
75  printf("\n TEST_DMA_BURST_8BIT");
76  ByteMode=1;
77  DconValue=(DMA0_HANDSHAKE_MODE|DMA0_SYNC_AHB|DMA0_DONE_GEN_INT|
78  DMA0_TSZ_BURST|DMA0_WHOLE_SVC|DMA0_SW_TRIG|
79  DMA0_RELOAD_OFF|DMA0_DSZ_8b);
80  }
81  else if(TestDmaCtrl.TestMode==TEST_DMA_BURST_16BIT){
82  printf("\n TEST_DMA_BURST_16BIT");
83  ByteMode=2;
84  DconValue=(DMA0_HANDSHAKE_MODE|DMA0_SYNC_AHB|DMA0_DONE_GEN_INT|
85  DMA0_TSZ_BURST|DMA0_WHOLE_SVC|DMA0_SW_TRIG|
86  DMA0_RELOAD_OFF|DMA0_DSZ_16b);
87  }
88  else if(TestDmaCtrl.TestMode==TEST_DMA_BURST_32BIT){
89  printf("\n TEST_DMA_BURST_32BIT");
90  ByteMode=4;
91  DconValue=(DMA0_HANDSHAKE_MODE|DMA0_SYNC_AHB|DMA0_DONE_GEN_INT|
92  DMA0_TSZ_BURST|DMA0_WHOLE_SVC|DMA0_SW_TRIG|
93  DMA0_RELOAD_OFF|DMA0_DSZ_32b);
94  }
95  else{
96  printf("\n TEST_DMA_BURST_8BIT");
97  ByteMode=1;
98  DconValue=(DMA0_HANDSHAKE_MODE|DMA0_SYNC_AHB|DMA0_DONE_GEN_INT|
99  DMA0_TSZ_BURST|DMA0_WHOLE_SVC|DMA0_SW_TRIG|
100  DMA0_RELOAD_OFF|DMA0_DSZ_8b);
101  }
102  F_Dma0Allocate(TestDmaCtrl.Id);
103  F_Dma0DisrcSet(TestDmaCtrl.Id,TEST_DMA_SOURCE_ADDR);
104  F_Dma0DisrccSet(TestDmaCtrl.Id,(DMA0_SRC_LOC_AHB|DMA0_SRC_ADDR_INC));
105  F_Dma0DidstSet(TestDmaCtrl.Id,TEST_DMA_DESTINATION_ADR);
106  F_Dma0DidstcSet(TestDmaCtrl.Id,(DMA0_DST_LOC_AHB|DMA0_SRC_ADDR_INC));
107  F_Dma0DconSet(TestDmaCtrl.Id,DconValue|(TEST_DMA_DATA_LENGTH/ByteMode));
108  //F_Dma0LengthSet(TestDmaCtrl.Id,TEST_DMA_DATA_LENGTH/2); // 0x800/2...16bit mode
109  F_Dma0TriggerModeSet(TestDmaCtrl.Id,DMA0_TRIGGER_SW);
110  F_Dma0IsrHookFunctionSet(TestDmaCtrl.Id,(INT32U)TestDmaDma0Isr); //pISR_DMA0=(INT32U)TestDmaDma0Isr;
111  F_InterruptIrqEnable(BIT_DMA0);
112  TestDmaCtrl.InTransfer=TRUE; // set transfer flag...clear in isr
113  F_Dma0Start(TestDmaCtrl.Id); // start dma
114  TestDmaCtrl.State=TestDmaDma0State1;
115  break;
116  case TestDmaDma0State1:
117  if(TestDmaCtrl.InTransfer==TRUE) return;
118  F_Dma0Release(TestDmaCtrl.Id);
119  F_InterruptIrqDisable(BIT_DMA0);
120  TestDmaCtrl.State=TestDmaIdleState;
121  break;
122  case TestDmaDma1State0:
123  if(F_Dma1InUseCheck()==TRUE) return;
124  //DconValue=(DMA1_HANDSHAKE_MODE|DMA1_SYNC_AHB|DMA1_DONE_GEN_INT|
125  // DMA1_TSZ_UNIT|DMA1_SINGLE_SVC|DMA1_SW_TRIG|
126  // DMA1_RELOAD_OFF|DMA1_DSZ_16b)|(DMA1_IISSDO<<24);
127 
128  DconValue=(DMA1_HANDSHAKE_MODE|DMA1_SYNC_AHB|DMA1_DONE_GEN_INT|
129  DMA1_TSZ_BURST|DMA1_WHOLE_SVC|DMA1_SW_TRIG|
130  DMA1_RELOAD_OFF|DMA1_DSZ_16b);
131  F_Dma1Allocate(TestDmaCtrl.Id);
132  F_Dma1DisrcSet(TestDmaCtrl.Id,TEST_DMA_SOURCE_ADDR);
133  F_Dma1DisrccSet(TestDmaCtrl.Id,(DMA1_SRC_LOC_AHB|DMA1_SRC_ADDR_INC));
134  F_Dma1DidstSet(TestDmaCtrl.Id,TEST_DMA_DESTINATION_ADR);
135  F_Dma1DidstcSet(TestDmaCtrl.Id,(DMA1_DST_LOC_AHB|DMA1_SRC_ADDR_INC));
136  F_Dma1DconSet(TestDmaCtrl.Id,DconValue|(TEST_DMA_DATA_LENGTH/2));
137  //F_Dma1LengthSet(TestDmaCtrl.Id,TEST_DMA_DATA_LENGTH/2); // 0x800/2...16bit mode
138  F_Dma1TriggerModeSet(TestDmaCtrl.Id,DMA1_TRIGGER_SW);
139  F_Dma1IsrHookFunctionSet(TestDmaCtrl.Id,(INT32U)TestDmaDma1Isr); //pISR_DMA1=(INT32U)TestDmaDma1Isr;
140  F_InterruptIrqEnable(BIT_DMA1);
141  TestDmaCtrl.InTransfer=TRUE; // set transfer flag...clear in isr
142  F_Dma1Start(TestDmaCtrl.Id); // start dma
143  TestDmaCtrl.State=TestDmaDma1State1;
144  break;
145  case TestDmaDma1State1:
146  if(TestDmaCtrl.InTransfer==TRUE) return;
147  F_Dma1Release(TestDmaCtrl.Id);
148  F_InterruptIrqDisable(BIT_DMA1);
149  TestDmaCtrl.State=TestDmaIdleState;
150  break;
151  case TestDmaDma2State0:
152  if(F_Dma2InUseCheck()==TRUE) return;
153  //DconValue=(DMA2_HANDSHAKE_MODE|DMA2_SYNC_AHB|DMA2_DONE_GEN_INT|
154  // DMA2_TSZ_UNIT|DMA2_SINGLE_SVC|DMA2_SW_TRIG|
155  // DMA2_RELOAD_OFF|DMA2_DSZ_16b)|(DMA2_IISSDO<<24);
156 
157  DconValue=(DMA2_HANDSHAKE_MODE|DMA2_SYNC_AHB|DMA2_DONE_GEN_INT|
158  DMA2_TSZ_BURST|DMA2_WHOLE_SVC|DMA2_SW_TRIG|
159  DMA2_RELOAD_OFF|DMA2_DSZ_16b);
160  F_Dma2Allocate(TestDmaCtrl.Id);
161  F_Dma2DisrcSet(TestDmaCtrl.Id,TEST_DMA_SOURCE_ADDR);
162  F_Dma2DisrccSet(TestDmaCtrl.Id,(DMA2_SRC_LOC_AHB|DMA2_SRC_ADDR_INC));
163  F_Dma2DidstSet(TestDmaCtrl.Id,TEST_DMA_DESTINATION_ADR);
164  F_Dma2DidstcSet(TestDmaCtrl.Id,(DMA2_DST_LOC_AHB|DMA2_SRC_ADDR_INC));
165  F_Dma2DconSet(TestDmaCtrl.Id,DconValue|(TEST_DMA_DATA_LENGTH/2));
166  //F_Dma2LengthSet(TestDmaCtrl.Id,TEST_DMA_DATA_LENGTH/2); // 0x800/2...16bit mode
167  F_Dma2TriggerModeSet(TestDmaCtrl.Id,DMA2_TRIGGER_SW);
168  F_Dma2IsrHookFunctionSet(TestDmaCtrl.Id,(INT32U)TestDmaDma2Isr); //pISR_DMA2=(INT32U)TestDmaDma2Isr;
169  F_InterruptIrqEnable(BIT_DMA2);
170  TestDmaCtrl.InTransfer=TRUE; // set transfer flag...clear in isr
171  F_Dma2Start(TestDmaCtrl.Id); // start dma
172  TestDmaCtrl.State=TestDmaDma2State1;
173  break;
174  case TestDmaDma2State1:
175  if(TestDmaCtrl.InTransfer==TRUE) return;
176  F_Dma2Release(TestDmaCtrl.Id);
177  F_InterruptIrqDisable(BIT_DMA2);
178  TestDmaCtrl.State=TestDmaIdleState;
179  break;
180  case TestDmaDma3State0:
181  if(F_Dma3InUseCheck()==TRUE) return;
182  //DconValue=(DMA3_HANDSHAKE_MODE|DMA3_SYNC_AHB|DMA3_DONE_GEN_INT|
183  // DMA3_TSZ_UNIT|DMA3_SINGLE_SVC|DMA3_SW_TRIG|
184  // DMA3_RELOAD_OFF|DMA3_DSZ_16b)|(DMA3_IISSDO<<24);
185 
186  DconValue=(DMA3_HANDSHAKE_MODE|DMA3_SYNC_AHB|DMA3_DONE_GEN_INT|
187  DMA3_TSZ_BURST|DMA3_WHOLE_SVC|DMA3_SW_TRIG|
188  DMA3_RELOAD_OFF|DMA3_DSZ_16b);
189  F_Dma3Allocate(TestDmaCtrl.Id);
190  F_Dma3DisrcSet(TestDmaCtrl.Id,TEST_DMA_SOURCE_ADDR);
191  F_Dma3DisrccSet(TestDmaCtrl.Id,(DMA3_SRC_LOC_AHB|DMA3_SRC_ADDR_INC));
192  F_Dma3DidstSet(TestDmaCtrl.Id,TEST_DMA_DESTINATION_ADR);
193  F_Dma3DidstcSet(TestDmaCtrl.Id,(DMA3_DST_LOC_AHB|DMA3_SRC_ADDR_INC));
194  F_Dma3DconSet(TestDmaCtrl.Id,DconValue|(TEST_DMA_DATA_LENGTH/2));
195  //F_Dma3LengthSet(TestDmaCtrl.Id,TEST_DMA_DATA_LENGTH/2); // 0x800/2...16bit mode
196  F_Dma3TriggerModeSet(TestDmaCtrl.Id,DMA3_TRIGGER_SW);
197  F_Dma3IsrHookFunctionSet(TestDmaCtrl.Id,(INT32U)TestDmaDma3Isr); //pISR_DMA3=(INT32U)TestDmaDma3Isr;
198  F_InterruptIrqEnable(BIT_DMA3);
199  TestDmaCtrl.InTransfer=TRUE; // set transfer flag...clear in isr
200  F_Dma3Start(TestDmaCtrl.Id); // start dma
201  TestDmaCtrl.State=TestDmaDma3State1;
202  break;
203  case TestDmaDma3State1:
204  if(TestDmaCtrl.InTransfer==TRUE) return;
205  F_Dma3Release(TestDmaCtrl.Id);
206  F_InterruptIrqDisable(BIT_DMA3);
207  TestDmaCtrl.State=TestDmaIdleState;
208  break;
209  }
210 }
211 INT8U F_TestDmaStatusCheck(void){
212  if(TestDmaCtrl.State==TestDmaIdleState) return TRUE;
213  else return FALSE;
214 }
215 INT8U F_TestDmaStart(INT8U DmaNumber){
216  if(DmaNumber==0){
217  TestDmaCtrl.State=TestDmaDma0State0;
218  return TRUE;
219  }
220  else if(DmaNumber==1){
221  TestDmaCtrl.State=TestDmaDma1State0;
222  return TRUE;
223  }
224  else if(DmaNumber==2){
225  TestDmaCtrl.State=TestDmaDma2State0;
226  return TRUE;
227  }
228  else if(DmaNumber==3){
229  TestDmaCtrl.State=TestDmaDma3State0;
230  return TRUE;
231  }
232  return FALSE;
233 }
234 void __irq TestDmaDma0Isr(void){
235  ClearPending(BIT_DMA0); //Clear pending bit
236  TestDmaCtrl.InTransfer=FALSE;
237 }
238 void __irq TestDmaDma1Isr(void){
239  ClearPending(BIT_DMA1); //Clear pending bit
240  TestDmaCtrl.InTransfer=FALSE;
241 }
242 void __irq TestDmaDma2Isr(void){
243  ClearPending(BIT_DMA2); //Clear pending bit
244  TestDmaCtrl.InTransfer=FALSE;
245 }
246 void __irq TestDmaDma3Isr(void){
247  ClearPending(BIT_DMA3); //Clear pending bit
248  TestDmaCtrl.InTransfer=FALSE;
249 }
250 
251 
252 
Generated on Wed Jun 13 2012 00:03:08 for BOOTLOADER by   doxygen 1.8.1.1