A Simple operation System using S3C2410: extdrivers/dm9000a.c Source File

00001 //========== 
00002 // Function: Driver of ethernet controller DM9000A
00003 // Author: Book Chen
00004 // Start time: 2007.06.04
00005 //==========
00006 #include "includes.h"
00007 
00008 #define Dm9000IdleState     0
00009 #define Dm9000InitialState0 1
00010 #define Dm9000InitialState1 2
00011 #define Dm9000InitialState2 3
00012 #define Dm9000InitialState3 4
00013 #define Dm9000InitialState4 5
00014 
00015 INT32U uiTemp;
00016 INT16U usiTemp;
00017 INT8U  ucTemp;
00018 DM9000_CONTROL Dm9000Ctrl;
00019 
00020 #define F_Dm9000ByteWrite(d,r) (*(volatile INT8U *)r=d)
00021 #define F_Dm9000WordWrite(d,r) (*(volatile INT16U *)r=d)
00022 #define F_Dm9000LongWrite(d,r) (*(volatile INT32U *)r=d)
00023 #define F_Dm9000ByteRead(r)    (*(volatile INT8U *)r)
00024 #define F_Dm9000WordRead(r)    (*(volatile INT16U *)r)
00025 #define F_Dm9000LongRead(r)    (*(volatile INT32U *)r)
00026 
00027 void F_Dm9000Init(void);
00028 void F_Dm9000Svc(void);
00029 BOOL F_Dm9000InUseCheck(void);
00030 BOOL F_Dm9000Allocate(INT16U UserId);
00031 BOOL F_Dm9000Release(INT16U UserId);  
00032 BOOL F_Dm9000InitialStart(INT16U UserId);
00033 void F_Dm9000Reset(void);    
00034 BOOL F_Dm9000Probe(void);
00035 void F_Dm9000ModeSet(INT8U Mode);
00036 BOOL F_Dm9000MacAddressSet(INT16U UserId,INT8U *pMacAddress);
00037 BOOL F_Dm9000IpAddressSet(INT16U UserId,INT8U *pIpAddress);
00038 BOOL F_Dm9000PacketTransmit(INT8U *pPacketData,INT16U PacketLength);
00039 INT32U F_Dm9000PacketReceive(INT8U *pPacketData,INT32U PacketLength);
00040 BOOL F_Dm9000PacketReceiveCheck(void);
00041 INT8U F_Dm9000IoRead(INT8U Address);    
00042 void F_Dm9000IoWrite(INT8U Address,INT8U Data);
00043 INT16U F_Dm9000PhyRead(INT8U RegisterAddr);
00044 void F_Dm9000PhyWrite(INT8U RegisterAddr,INT16U Value);
00045 
00046 void F_Dm9000Init(void){
00047     Dm9000Ctrl.InitialPass=FALSE;
00048     Dm9000Ctrl.IoBase=DM9000_ADDRESS;
00049     Dm9000Ctrl.MemBase=0;
00050     Dm9000Ctrl.LinkType=DM9000_LINK_UNKNOW;
00051     //Dm9000Ctrl.Id=ID_DM9000;
00052     Dm9000Ctrl.InUse=FALSE;    
00053     Dm9000Ctrl.State=Dm9000IdleState;                                                                      
00054 }    
00055 void F_Dm9000Svc(void){
00056     INT8U i;
00057     switch(Dm9000Ctrl.State){
00058         case Dm9000IdleState:
00059             break;
00060         case Dm9000InitialState0:
00061             F_Dm9000Probe();
00062             F_Dm9000Reset();
00063             F_Dm9000ModeSet(DM9000_AUTO); // set phy operation mode
00064             F_Dm9000IoWrite(DM9000_NCR,0x0);        // only intern phy supported by now 
00065             F_Dm9000IoWrite(DM9000_TCR,0);      // tx polling clear 
00066             F_Dm9000IoWrite(DM9000_BPTR,0x3f);  // Less 3Kb, 200us 
00067             F_Dm9000IoWrite(DM9000_SMCR,0);     // special mode 
00068             F_Dm9000IoWrite(DM9000_NSR,(NSR_WAKEST|NSR_TX2END |NSR_TX1END));    // clear tx status 
00069             F_Dm9000IoWrite(DM9000_ISR,0x0f);   // clear interrupt status 
00070             i=0x10;
00071             for(ucTemp=0;ucTemp<6;ucTemp++) F_Dm9000IoWrite(i++,Dm9000Ctrl.MacAddress[ucTemp]);
00072             i=0x16;
00073             for(ucTemp=0;ucTemp<8;ucTemp++) F_Dm9000IoWrite(i++,0xff);
00074             F_Dm9000IoWrite(DM9000_RCR,(RCR_DIS_LONG|RCR_DIS_CRC|RCR_RXEN)); // rx enable 
00075             F_Dm9000IoWrite(DM9000_IMR,0xa3);   
00076             for(uiTemp=0;uiTemp<10000;uiTemp++){
00077                 if(F_Dm9000PhyRead(DM9000_PHY_STATUS)&BIT_AUTO_N_COMPL) break;                      
00078             }
00079             if(uiTemp>=10000){
00080                 Dm9000Ctrl.State=Dm9000IdleState;               
00081                 Dm9000Ctrl.Status=FALSE;
00082                 return;
00083             }    
00084             usiTemp=F_Dm9000PhyRead(DM9000_PHY_SCS)>>12;
00085             switch(usiTemp){
00086                 case 1:
00087                    Dm9000Ctrl.LinkType=DM9000_LINK_10HDX;
00088                    break;
00089                 case 2:
00090                    Dm9000Ctrl.LinkType=DM9000_LINK_10FDX;
00091                    break;
00092                 case 3:
00093                    Dm9000Ctrl.LinkType=DM9000_LINK_100HDX;
00094                    break;
00095                 case 4:
00096                    Dm9000Ctrl.LinkType=DM9000_LINK_100FDX;
00097                    break;
00098                 default:
00099                    Dm9000Ctrl.LinkType=DM9000_LINK_UNKNOW;
00100                    break;
00101             }
00102             Dm9000Ctrl.State=Dm9000InitialState1;
00103             break;
00104         case Dm9000InitialState1:
00105             Dm9000Ctrl.State=Dm9000InitialState2;
00106             break;
00107         case Dm9000InitialState2:
00108             Dm9000Ctrl.State=Dm9000InitialState3;
00109             break;
00110         case Dm9000InitialState3:
00111             Dm9000Ctrl.State=Dm9000InitialState4;
00112             break;
00113         case Dm9000InitialState4:
00114             Dm9000Ctrl.State=Dm9000IdleState;
00115             break;
00116     }
00117 }
00118 INT8U F_Dm9000InUseCheck(void){
00119     if(Dm9000Ctrl.InUse==TRUE) return TRUE;
00120     else return FALSE;
00121 }
00122 INT8U F_Dm9000Allocate(INT16U UserId){
00123     if(Dm9000Ctrl.InUse==FALSE){
00124         Dm9000Ctrl.InUse=TRUE;        
00125         Dm9000Ctrl.UserId=UserId;
00126         return TRUE;
00127     }
00128     else return FALSE;
00129 }
00130 INT8U F_Dm9000Release(INT16U UserId){
00131     if((Dm9000Ctrl.InUse==TRUE)&&(Dm9000Ctrl.UserId==UserId)){
00132         Dm9000Ctrl.InUse=FALSE;
00133         return TRUE;
00134     }
00135     else return FALSE;
00136 }
00137 INT8U F_Dm9000InitialStart(INT16U UserId){
00138     if((Dm9000Ctrl.InUse==TRUE)&&(Dm9000Ctrl.UserId==UserId)){
00139         Dm9000Ctrl.State=Dm9000InitialState0;   
00140         return TRUE;
00141     }
00142     else return FALSE;
00143 }
00144 void F_Dm9000Reset(void){      
00145     // set the internal PHY power-on, GPIOs normal, and wait 2ms 
00146     F_Dm9000IoWrite(DM9000_GPR,1);            // power-down phy 
00147     for(uiTemp=0;uiTemp<20000;uiTemp++);  // cpu 400mhz...500us=400x500 (i guess)
00148     F_Dm9000IoWrite(DM9000_GPR,0);            // GPR (reg_1Fh)bit GPIO0=0 pre-activate PHY 
00149     for(uiTemp=0;uiTemp<80000;uiTemp++);  // wait 2ms for PHY power-on ready 
00150     F_Dm9000IoWrite(DM9000_NCR,3);  
00151     for(uiTemp=0;uiTemp<8000;uiTemp++);   // delay 20us 
00152     F_Dm9000IoWrite(DM9000_NCR,3);
00153     for(uiTemp=0;uiTemp<40000;uiTemp++); // delay 1ms   
00154 }
00155 BOOL F_Dm9000Probe(void){
00156     INT32U IdValue;
00157     
00158     IdValue=F_Dm9000IoRead(DM9000_VIDL);
00159     IdValue=(F_Dm9000IoRead(DM9000_VIDH)&0xff)<<8;
00160     IdValue=(F_Dm9000IoRead(DM9000_PIDL)&0xff)<<16;
00161     IdValue=(F_Dm9000IoRead(DM9000_PIDL)&0xff)<<24;
00162     if(IdValue==DM9000_ID) return TRUE;
00163     else return FALSE;
00164 }
00165 void F_Dm9000ModeSet(INT8U Mode){
00166     switch(Mode){
00167         default:
00168         case DM9000_AUTO:
00169             F_Dm9000PhyWrite(0,0x1200); 
00170             F_Dm9000PhyWrite(4,0x01e1); 
00171             break;
00172         case DM9000_10MHD:
00173             F_Dm9000PhyWrite(0,0x1000); 
00174             F_Dm9000PhyWrite(4,0x0021); 
00175             break;
00176         case DM9000_10MFD:
00177             F_Dm9000PhyWrite(0,0x1100); 
00178             F_Dm9000PhyWrite(4,0x0041); 
00179             break;
00180         case DM9000_100MHD:
00181             F_Dm9000PhyWrite(0,0x3000); 
00182             F_Dm9000PhyWrite(4,0x0081); 
00183             break;
00184         case DM9000_100MFD: 
00185             F_Dm9000PhyWrite(0,0x3100); 
00186             F_Dm9000PhyWrite(4,0x0101); 
00187             break;   
00188     }
00189 }
00190 INT8U F_Dm9000MacAddressSet(INT16U UserId,INT8U *pMacAddress){
00191     if((Dm9000Ctrl.InUse==TRUE)&&(Dm9000Ctrl.UserId==UserId)){
00192         Dm9000Ctrl.MacAddress[0]=pMacAddress[0];
00193         Dm9000Ctrl.MacAddress[1]=pMacAddress[1];
00194         Dm9000Ctrl.MacAddress[2]=pMacAddress[2];
00195         Dm9000Ctrl.MacAddress[3]=pMacAddress[3];
00196         Dm9000Ctrl.MacAddress[4]=pMacAddress[4];
00197         Dm9000Ctrl.MacAddress[5]=pMacAddress[5];
00198         return TRUE;
00199     }
00200     else return FALSE;
00201 }
00202 INT8U F_Dm9000IpAddressSet(INT16U UserId,INT8U *pIpAddress){
00203     if((Dm9000Ctrl.InUse==TRUE)&&(Dm9000Ctrl.UserId==UserId)){
00204         Dm9000Ctrl.IpAddress[0]=pIpAddress[0];
00205         Dm9000Ctrl.IpAddress[1]=pIpAddress[1];
00206         Dm9000Ctrl.IpAddress[2]=pIpAddress[2];
00207         Dm9000Ctrl.IpAddress[3]=pIpAddress[3];
00208         return TRUE;
00209     }
00210     else return FALSE;
00211 }
00212 BOOL F_Dm9000PacketTransmit(INT8U *pPacketData,INT16U PacketLength){
00213     INT16U *pData;
00214     INT16U TxLength;
00215     
00216     F_Dm9000ByteWrite(DM9000_MWCMD,DM9000_IO);
00217     pData=(INT16U *)pPacketData;
00218     TxLength=(PacketLength+1)/2;
00219     for(uiTemp=0;uiTemp<TxLength;uiTemp++) F_Dm9000ByteWrite(*pData++,DM9000_DATA);     
00220     F_Dm9000IoWrite(DM9000_TXPLH,(PacketLength>>8)&0xff); // set tx length
00221     F_Dm9000IoWrite(DM9000_TXPLL,PacketLength&0xff);
00222     F_Dm9000IoWrite(DM9000_TCR, TCR_TXREQ); // cleared after tx complete 
00223     uiTemp=0;
00224     while(F_Dm9000IoRead(DM9000_TCR)&TCR_TXREQ){ 
00225         if(uiTemp>=1000000) return FALSE; // time out
00226         uiTemp++;        
00227     }
00228     return TRUE;
00229 }
00230 INT32U F_Dm9000PacketReceive(INT8U *pPacketData,INT32U PacketLength){
00231     INT8U RxByte;
00232     INT16U RxStatus,RxLength;
00233     INT16U *pData;    
00234         
00235     F_Dm9000IoRead(DM9000_MRCMDX);
00236     F_Dm9000IoRead(DM9000_MRRH); //??
00237     F_Dm9000IoRead(DM9000_MRRL); //??
00238     RxByte=F_Dm9000IoRead(DM9000_MRCMDX);
00239     if(RxByte==0) return FALSE;
00240     //else if(RxByte==DM9000_PACKET_READY);
00241     else if(RxByte>1){ // 1 only
00242         F_Dm9000IoWrite(DM9000_RCR,0x00);
00243         F_Dm9000IoWrite(DM9000_ISR,0x80); 
00244         F_Dm9000Reset();
00245         return FALSE;
00246     }        
00247     F_Dm9000ByteWrite(DM9000_MRCMD, DM9000_IO);
00248     RxStatus=F_Dm9000WordRead(DM9000_DATA);
00249     RxLength=F_Dm9000WordRead(DM9000_DATA);
00250     if((RxStatus&0xbf00)||(RxLength<64)||(RxLength>PacketLength)){
00251         if(RxStatus&0x0100); // rx fifo error
00252         if(RxStatus&0x0200); // rx crc error
00253         if(RxStatus&0x8000); // rx length error
00254         if(RxLength>PacketLength) F_Dm9000Reset();
00255         return 0; // reutrn length 0...no data
00256     }    
00257     pData=(INT16U *)pPacketData;
00258     usiTemp=(RxLength+1)/2;
00259     for(uiTemp=0;uiTemp<usiTemp;uiTemp++) 
00260         *pData++=F_Dm9000WordRead(DM9000_DATA);
00261     return (INT32U)RxLength;    
00262 }
00263 BOOL F_Dm9000PacketReceiveCheck(void){
00264     INT8U RxByte;
00265    
00266     F_Dm9000IoRead(DM9000_MRCMDX);
00267     F_Dm9000IoRead(DM9000_MRRH); 
00268     F_Dm9000IoRead(DM9000_MRRL);
00269     RxByte=F_Dm9000IoRead(DM9000_MRCMDX);
00270     if(RxByte==0) return FALSE; // no rx data
00271     /*else if(RxByte==DM9000_PACKET_READY) return TRUE;
00272     else {
00273         F_Dm9000IoWrite(DM9000_RCR,0x00);
00274         F_Dm9000IoWrite(DM9000_ISR,0x80); 
00275         F_Dm9000Reset();
00276         return FALSE;
00277     }*/   
00278     else return TRUE;
00279 }
00280 INT8U F_Dm9000IoRead(INT8U Address){
00281     F_Dm9000ByteWrite(Address,DM9000_IO);
00282     return F_Dm9000ByteRead(DM9000_DATA);
00283 }
00284 void F_Dm9000IoWrite(INT8U Address,INT8U Data){
00285     F_Dm9000ByteWrite(Address,DM9000_IO);    
00286     F_Dm9000ByteWrite(Data,DM9000_DATA);
00287 }
00288 INT16U F_Dm9000PhyRead(INT8U RegisterAddr){ // access phy registers
00289     INT16U Value;
00290         
00291     F_Dm9000IoWrite(DM9000_EPAR,DM9000_PHY|RegisterAddr); // set phy status register addr in EPAR reg.
00292     F_Dm9000IoWrite(DM9000_EPCR,0xc);    // set phy read command  
00293     for(uiTemp=0;uiTemp<40000;uiTemp++); // wait read command complete 
00294     Value=((F_Dm9000IoRead(DM9000_EPDRH)&0xff)<<8)|(F_Dm9000IoRead(DM9000_EPDRL)&0xff); 
00295     F_Dm9000IoWrite(DM9000_EPCR,0x0);    // Clear phyxcer read command ??   
00296     return Value;
00297 }
00298 void F_Dm9000PhyWrite(INT8U RegisterAddr,INT16U Value){    
00299     F_Dm9000IoWrite(DM9000_EPAR,DM9000_PHY|RegisterAddr); // Fill the phyxcer register into REG_0C  
00300     F_Dm9000IoWrite(DM9000_EPDRL,(Value&0xff));  // Fill the written data into REG_0D & REG_0E 
00301     F_Dm9000IoWrite(DM9000_EPDRH,((Value>>8)&0xff));
00302     F_Dm9000IoWrite(DM9000_EPCR,0xa);              // set phy write command 
00303     for(uiTemp=0;uiTemp<200000;uiTemp++);          // Wait write command complete 
00304     F_Dm9000IoWrite(DM9000_EPCR,0x0);              // Clear phyxcer write command 
00305 }
00306 
00307 
00308