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00010 #include "asm_linkage.h"
00011 #include "s3c2440.h"
00012 #include "asm_sizes.h"
00013 #include "system/smdk2440.h"
00014
00015 .extern Main
00016
00017 .extern OSTCBCur @ current task control block pointer
00018 .extern OSTCBHighRdy @ next task control block pointer
00019 .extern OSPrioCur @ current task id
00020 .extern OSPrioHighRdy @ next task id
00021 .extern OSIntNesting @ nested interrupt counter
00022 .extern OSRunning @ operation system running flag
00023
00024 .extern OSStartHighRdy @ Os starts to run highest priority task
00025 .extern OSCtxSw @ Os task level context switch
00026 .extern OSIntCtxSw @ Os interrupt level context switch
00027 .extern OS_ENTER_CRITICAL @ Enter os critical section
00028 .extern OS_EXIT_CRITICAL @ Exit os critical section
00029
00030 @ exception handle
00031 .globl HandleReset
00032 .globl HandleUndef
00033 .globl HandleSWI
00034 .globl HandlePabort
00035 .globl HandleDabort
00036 .globl HandleReserved
00037 .globl HandleIRQ
00038 .globl HandleFIQ
00039 @ irq handle
00040 .globl HandleEINT0
00041 .globl HandleEINT1
00042 .globl HandleEINT2
00043 .globl HandleEINT3
00044 .globl HandleEINT4_7
00045 .globl HandleEINT8_23
00046 .globl HandleCAM
00047 .globl HandleBATFLT
00048 .globl HandleTICK
00049 .globl HandleWDT
00050 .globl HandleTimer0
00051 .globl HandleTimer1
00052 .globl HandleTimer2
00053 .globl HandleTimer3
00054 .globl HandleTimer4
00055 .globl HandleUART2
00056 .globl HandleLCD
00057 .globl HandleDMA0
00058 .globl HandleDMA1
00059 .globl HandleDMA2
00060 .globl HandleDMA3
00061 .globl HandleMMC
00062 .globl HandleTICK
00063 .globl HandleSPI0
00064 .globl HandleUART1
00065 .globl HandleNFCON
00066 .globl HandleUSBD
00067 .globl HandleUSBH
00068 .globl HandleIIC
00069 .globl HandleUART0
00070 .globl HandleSPI1
00071 .globl HandleRTC
00072 .globl HandleADC
00073
00074 .equ SystemStack ,0x33ff4800
00075 .equ SVCStack ,0x33ff5800
00076 .equ UndefStack ,0x33ff5c00
00077 .equ AbortStack ,0x33ff6000
00078 .equ IRQStack ,0x33ff7000
00079 .equ FIQStack ,0x33ff8000
00080
00081 .equ USERMODE ,0x10
00082 .equ FIQMODE ,0x11
00083 .equ IRQMODE ,0x12
00084 .equ SVCMODE ,0x13
00085 .equ ABORTMODE ,0x17
00086 .equ UNDEFMODE ,0x1b
00087 .equ SYSTEMMODE ,0x1f
00088 .equ MODEMASK ,0x1f
00089 .equ NOINT ,0xc0
00090
00091 ENTRY(_start)
00092 ENTRY(ResetEntryPoint)
00093 @Exception vector table (physical address = 0x00000000)
00094 ldr pc,ExceptionVectors+0x00
00095 ldr pc,ExceptionVectors+0x04
00096 ldr pc,ExceptionVectors+0x08
00097 ldr pc,ExceptionVectors+0x0c
00098 ldr pc,ExceptionVectors+0x10
00099 ldr pc,ExceptionVectors+0x14
00100 ldr pc,ExceptionVectors+0x18
00101 ldr pc,ExceptionVectors+0x1c
00102
00103 @ VIVI magics
00104 .long 0 @ 0x20: #include "platform/smdk2440.h"
00105 .long 0 @ 0x24:
00106 .long _start @ 0x28:
00107 .long 0x1234567 @ 0x2C: this contains the platform, cpu and machine id
00108 .long 0 @ 0x30: vivi capabilities
00109 #ifdef CONFIG_PM
00110 b SleepRamProc @ 0x34:
00111 #endif
00112
00113
00114 .align 4
00115 ExceptionVectors:
00116 .long HandlerReset
00117 .long HandlerUndef
00118 .long HandlerSWI
00119 .long HandlerPrefetchAbort
00120 .long HandlerDataAbort
00121 .long HandlerReserved
00122 .long HandlerIrq
00123 .long HandlerFiq
00124
00125 @Exception handlers
00126 HandlerReserved: b .
00127 HandlerUndef: b .
00128 HandlerSWI: b .
00129 HandlerPrefetchAbort: b .
00130 HandlerDataAbort: b .
00131 HandlerFiq: b .
00132 HandlerIrq:
00133 sub lr,lr,#4 @ lr=lr-4
00134 stmfd sp!,{r0-r12,lr} @ Push r0-r12,lr into stack
00135 ldr r0,=OSIntNesting @ OSIntNesting++
00136 ldrb r1,[r0] @ OSIntNesting++
00137 add r1,r1,#1 @ OSIntNesting++
00138 strb r1,[r0] @ OSIntNesting++
00139 ldr lr,=HandlerIrqExit+4 @ Set irq hook function return address
00140 mrs r0,spsr
00141 stmfd sp!,{r0} @ Push irq mode spsr...it is svc cpsr before enter irq
00142 mrs r0,cpsr
00143 msr spsr_cxsf,r0 @ Let spsr=cpsr
00144 ldr r0,=HandleEINT0 @
00145 ldr r1,=INTOFFSET @
00146 ldr r1,[r1] @
00147 add r0,r0,r1,lsl #2 @ r0 = r0 + r1*4
00148 ldr pc,[r0] @ call irq hook function
00149 HandlerIrqExit:
00150 mrs r0,cpsr
00151 orr r0,r0,#NOINT
00152 msr cpsr_cxsf,r0 @ disable irq,fiq
00153 ldmfd sp!,{r0}
00154 msr spsr_cxsf,r0 @ Pop back spsr
00155
00156 ldr r0,=OSIntNesting @ check interrupt nesting
00157 ldrb r1,[r0]
00158 subs r1,r1,#1
00159 str r1,[r0]
00160 ldr r0,=0
00161 cmp r1,r0
00162 ldrne pc,=L_NoDoTaskSwitch @ not 1st level interrupt nest...no do csw
00163
00164 ldr r0,=OSTaskSwitch @ ckeck task switch
00165 ldr r0,[r0]
00166 ldr r1,=0
00167 cmp r0,r1
00168 ldreq pc,=L_NoDoTaskSwitch @ no task switch flag...no do csw
00169
00170 ldr r0,=OSTaskSwitch
00171 ldr r1,=0
00172 str r1,[r0] @ clear OSTaskSwitch flag
00173 ldmfd sp!,{r0-r12,lr} @ pop back r0-r12,lr
00174 ldr pc,=OSIntCtxSw @ do interrupt level context switch
00175
00176 L_NoDoTaskSwitch:
00177 ldmfd sp!,{r0-r12,pc}^ @cpsr=spsr...return from irq mode to system mode
00178
00179 HandlerReset:
00180 mov r1, #0x53000000 @ disable watch dog timer
00181 mov r2, #0x0
00182 str r2, [r1]
00183 mov r1, #INT_CTL_BASE @ disable all interrupts
00184 mov r2, #0xffffffff
00185 str r2, [r1, #oINTMSK]
00186 ldr r2, =0x7ff
00187 str r2, [r1, #oINTSUBMSK]
00188
00189 .myplace:
00190 mov r1, #CLK_CTL_BASE @ initialise system clocks
00191 mvn r2, #0xff000000
00192 str r2, [r1, #oLOCKTIME]
00193
00194 mov r1, #CLK_CTL_BASE
00195 ldr r2, clkdivn_value @ 5...1:4:8 clock diveider setting for fclk:hclk:pclk
00196 str r2, [r1, #oCLKDIVN]
00197
00198 mrc p15, 0, r1, c1, c0, 0 @ read ctrl register
00199 orr r1, r1, #0xc0000000 @ Asynchronous
00200 mcr p15, 0, r1, c1, c0, 0 @ write ctrl register
00201
00202 mov r1, #CLK_CTL_BASE
00203 ldr r2, mpll_value_USER @ clock user set 92:1:1
00204 str r2, [r1, #oMPLLCON] @
00205
00206 bl memsetup @ set memory access parameters
00207
00208 #ifdef CONFIG_PM
00209 @ Check if this is a wake-up from sleep
00210 ldr r1, PMST_ADDR
00211 ldr r0, [r1]
00212 tst r0, #(PMST_SMR)
00213 bne WakeupStart
00214 #endif
00215 @mov r1, #GPIO_CTL_BASE @ All LED on
00216 @add r1, r1, #oGPIO_F
00217 @ldr r2,=0x55aa
00218
00219 mrs r0,cpsr
00220 bic r0,r0,#(MODEMASK|NOINT)
00221
00222 orr r1,r0,#(UNDEFMODE|NOINT)
00223 msr cpsr_cxsf,r1 @UndefMode
00224 ldr sp,=UndefStack @UndefStack=0x33FF_5C00
00225
00226 orr r1,r0,#(ABORTMODE|NOINT)
00227 msr cpsr_cxsf,r1 @AbortMode
00228 ldr sp,=AbortStack @AbortStack=0x33FF_6000
00229
00230 orr r1,r0,#(IRQMODE|NOINT)
00231 msr cpsr_cxsf,r1 @IRQMode
00232 ldr sp,=IRQStack @IRQStack=0x33FF_7000
00233
00234 orr r1,r0,#(FIQMODE|NOINT)
00235 msr cpsr_cxsf,r1 @FIQMode
00236 ldr sp,=FIQStack @FIQStack=0x33FF_8000
00237
00238 orr r1,r0,#(SVCMODE|NOINT)
00239 msr cpsr_cxsf,r1 @SVCMode
00240 ldr sp,=SVCStack @SVCStack=0x33FF_5800
00241
00242 orr r1,r0,#(SYSTEMMODE|NOINT)
00243 msr cpsr_cxsf,r1 @SVCMode
00244 ldr sp,=SystemStack @SVCStack=0x33FF_5800
00245
00246 @USER mode has not be initialized.
00247 bl InitUART
00248 @bl copy_myself @ copy the rest of code in nandflash...bookysc080817
00249 @ jump to ram
00250 ldr r1, =on_the_ram
00251 add pc, r1, #0
00252 nop
00253 nop
00254 1: b 1b @ infinite loop
00255 nop
00256 nop
00257 @.fpic:
00258 @ .long _start-(.myplace+8)
00259 on_the_ram:
00260 ldr sp, DW_STACK_START @ setup stack pointer
00261 mov fp, #0 @ no previous frame, so fp=0
00262 mov a2, #0 @ set argv to NULL
00263 bl Main @ call main
00264 b .
00265 @ mov pc, #FLASH_BASE @ otherwise, reboot
00266 @===========================
00267 @ subroutines
00268 @===========================
00269 @ Wake-up code
00270 #ifdef CONFIG_PM
00271 WakeupStart:
00272 @ Clear sleep reset bit
00273 ldr r0, PMST_ADDR
00274 mov r1, #PMST_SMR
00275 str r1, [r0]
00276
00277 @ Release the SDRAM signal protections
00278 ldr r0, PMCTL1_ADDR
00279 ldr r1, [r0]
00280 bic r1, r1, #(SCLKE | SCLK1 | UART0_CTL_BASESCLK0)
00281 str r1, [r0]
00282
00283 @ Go...
00284 ldr r0, PMSR0_ADDR @ read a return address
00285 ldr r1, [r0]
00286 mov pc, r1
00287 nop
00288 nop
00289 1: b 1b @ infinite loop
00290
00291 SleepRamProc:
00292 @ SDRAM is in the self-refresh mode
00293 ldr r0, REFR_ADDR
00294 ldr r1, [r0]
00295 orr r1, r1, #SELF_REFRESH
00296 str r1, [r0]
00297
00298 @ wait until SDRAM into self-refresh
00299 mov r1, #16
00300 1: subs r1, r1, #1
00301 bne 1b
00302
00303 @ Set the SDRAM singal protections
00304 ldr r0, PMCTL1_ADDR
00305 ldr r1, [r0]
00306 orr r1, r1, #(SCLKE | SCLK1 | SCLK0)
00307 str r1, [r0]
00308
00309 @ldr r2, =0x245 @ level int,rx error report,tx,rx
00310
00311 ldr r0, PMCTL0_ADDR
00312 ldr r1, [r0]
00313 orr r1, r1, #SLEEP_ON
00314 str r1, [r0]
00315 1: b 1b
00316
00317 #ifdef CONFIG_TEST
00318 hmi:
00319 ldr r0, PMCTL0_ADDR
00320 ldr r1, =0x7fff0
00321 str r1, [r0]
00322
00323 @ All LED onUART0_CTL_BASE
00324 mov r1, #GPIO_CTL_BASE
00325 add r1, r1, #oGPIO_F
00326 ldr r2,=0x55aa
00327 str r2, [r1, #oGPIO_CON]
00328 mov r2, #0xff
00329 str r2, [r1, #oGPIO_UP]
00330 mov r2, #0xe0
00331 str r2, [r1, #oGPIO_DAT]
00332 1: b 1b
00333 #endif
00334
00335 #endif
00336 @ initialise the static memory
00337 @ set memory control registers
00338 ENTRY(memsetup)
00339 mov r1, #MEM_CTL_BASE
00340 adrl r2, mem_cfg_val
00341 add r3, r1, #52
00342 1: ldr r4, [r2], #4
00343 str r4, [r1], #4
00344 cmp r1, r3
00345 bne 1b
00346 mov pc, lr
00347
00348 @ nandflash bootcode loader
00349 @ copy_myself: copy vivi to ram
00350 @
00351 copy_myself:
00352 stmfd sp!,{lr}
00353
00354 @ reset NAND
00355 mov r1, #NAND_CTL_BASE
00356 ldr r2, =( (7<<12)|(7<<8)|(7<<4)|(0<<0) )
00357 str r2, [r1, #oNFCONF]
00358 ldr r2, [r1, #oNFCONF]
00359
00360 ldr r2, =( (1<<4)|(0<<1)|(1<<0) ) @ Active low CE Control
00361 str r2, [r1, #oNFCONT]
00362 ldr r2, [r1, #oNFCONT]
00363
00364 ldr r2, =(0x6) @ RnB Clear
00365 str r2, [r1, #oNFSTAT]
00366 ldr r2, [r1, #oNFSTAT]
00367
00368 mov r2, #0xff @ RESET command
00369 strb r2, [r1, #oNFCMD]
00370 mov r2, #0 @ wait
00371 1: add r2, r2, #0x1
00372 cmp r2, #0xa
00373 blt 1b
00374 2: ldr r2, [r1, #oNFSTAT] @ wait ready
00375 tst r2, #0x4
00376 beq 2b
00377
00378 ldr r2, [r1, #oNFCONT]
00379 orr r2, r2, #0x2 @ Flash Memory Chip Disable
00380 str r2, [r1, #oNFCONT]
00381
00382 mov r1, #GPIO_CTL_BASE
00383 add r1, r1, #oGPIO_F
00384 mov r2, #0xe0
00385 str r2, [r1, #oGPIO_DAT]
00386
00387
00388 #ifndef CONFIG_S3C2440_NAND_BOOT
00389 ldr r2, =__bss_start
00390 ldr r0, =__ro_start
00391 mov r1, sl
00392 sub r2,r2,r0
00393 ldmfd sp!,{lr}
00394 b mem_copy
00395 #else @ #ifdef CONFIG_S3C2440_NAND_BOOT
00396 @ copy vivi to RAM
00397 @ldr r0, =VIVI_RAM_BASE
00398 @mov r1, #0x0
00399 @mov r2, #0x20000
00400 @mov r0, #'R'
00401 @bl PrintChar
00402
00403 ldr r2, =__bss_start
00404 ldr r0, =__ro_start
00405 movs r1, sl
00406 @mov r1, #0
00407 sub r2,r2,r0
00408 ldmnefd sp!,{lr}
00409 bne mem_copy
00410 bl nand_read_ll
00411
00412 #if 1
00413 mov r1, #GPIO_CTL_BASE
00414 add r1, r1, #oGPIO_F
00415 mov r2, #0xb0
00416 str r2, [r1, #oGPIO_DAT]
00417 #endif
00418
00419 teq r0, #0x0
00420 beq ok_nand_read
00421 #ifdef CONFIG_DEBUG_LL
00422 bad_nand_read:
00423 ldr r0, STR_FAIL
00424 ldr r1, SerBase
00425 bl PrintWord
00426 #endif
00427 @mov r0, #'1'
00428 @bl PrintChar
00429 1: b 1b @ infinite loop
00430
00431 ok_nand_read:
00432 @ verify
00433 mov r0, #0
00434 @mov r0, sl
00435 ldr r1, =__ro_start
00436 mov r2, #0x400 @ 4 bytes * 1024 = 4K-bytes
00437 go_next:
00438 ldr r3, [r0], #4
00439 ldr r4, [r1], #4
00440 teq r3, r4
00441 bne notmatch
00442 subs r2, r2, #4
00443 beq done_nand_read
00444 bne go_next
00445 notmatch:
00446
00447 mov r0, #'v'
00448 bl PrintChar
00449 1: b 1b
00450 done_nand_read:
00451
00452 #if 1
00453 mov r1, #GPIO_CTL_BASE
00454 add r1, r1, #oGPIO_F
00455 mov r2, #0x00
00456 str r2, [r1, #oGPIO_DAT]
00457 #endif
00458
00459 ldmfd sp!,{pc}
00460
00461 #endif @ CONFIG_S3C2440_NAND_BOOT
00462
00463 @ copy memory to
00464 @ r0: to address
00465 @ r1: from address
00466 @ r2: length
00467 mem_copy:
00468 1:
00469 ldmia r1!, {r3-r10}
00470 stmia r0!, {r3-r10}
00471 subs r2, r2, #(8 * 4)
00472 bgt 1b
00473
00474 mov pc, lr
00475
00476 @ clear memory
00477 @ r0: start address
00478 @ r1: length
00479 mem_clear:
00480 mov r2, #0
00481 mov r3, r2
00482 mov r4, r2
00483 mov r5, r2
00484 mov r6, r2
00485 mov r7, r2
00486 mov r8, r2
00487 mov r9, r2
00488
00489 clear_loop:
00490 stmia r0!, {r2-r9}
00491 subs r1, r1, #(8 * 4)
00492 bne clear_loop
00493 mov pc, lr
00494
00495 @ Initialize UART
00496 @ r0 = number of UART port
00497 InitUART:
00498 stmfd sp!,{lr}
00499 mov r1, #GPIO_CTL_BASE @ set GPIO for UART
00500 add r1, r1, #oGPIO_H
00501 ldr r2, gpio_con_uart
00502 str r2, [r1, #oGPIO_CON]
00503 ldr r2, gpio_up_uart
00504 str r2, [r1, #oGPIO_UP]
00505 ldr r1, SerBase
00506 mov r2, #0x0
00507 str r2, [r1, #oUFCON]
00508 str r2, [r1, #oUMCON]
00509 mov r2, #0x3 @ n.8.1
00510 str r2, [r1, #oULCON]
00511 @ldr r2, =0x245 @ level int,rx error report,tx,rx
00512 ldr r2, =0x05 @ tx,rx
00513 str r2, [r1, #oUCON]
00514 #define UART_BRD ((UART_PCLK / (UART_BAUD_RATE * 16)) - 1)
00515 mov r2, #UART_BRD @ set baudrate...include/plateform/smdk2440.h
00516 str r2, [r1, #oUBRDIV]
00517
00518 mov r3, #100
00519 mov r2, #0x0
00520 1: sub r3, r3, #0x1
00521 teq r2,r3
00522 bne 1b
00523
00524 #if 0
00525 mov r0, #'U'
00526 bl PrintChar
00527
00528 mov r0, #'0'
00529 bl PrintChar
00530
00531 mov r0, #'\r'
00532 bl PrintChar
00533
00534 mov r0, #'\n'
00535 ldmfd sp!,{lr}
00536 b PrintChar
00537 #endif
00538 ldmfd sp!,{pc}
00539
00540 .global PrintChar
00541 @
00542 @ Low Level Debug
00543 @
00544 @ PrintChar : prints the character in R0
00545 @ r0 contains the character
00546 @ r1 contains base of serial port
00547 @ writes ro with XXX, modifies r0,r1,r2
00548 @ TODO : write ro with XXX reg to error handling
00549 PrintChar:
00550 ldr r1, SerBase
00551 1:
00552 ldr r2, [r1, #oUTRSTAT]
00553 tst r2, #UTRSTAT_TX_EMPTY
00554 beq 1b
00555 str r0, [r1, #oUTXHL]
00556 mov pc, lr
00557
00558 @ Data Area
00559 @ Memory configuration values
00560 .align 4
00561 mem_cfg_val:
00562 .long vBWSCON
00563 .long vBANKCON0
00564 .long vBANKCON1
00565 .long vBANKCON2
00566 .long vBANKCON3
00567 .long vBANKCON4
00568 .long vBANKCON5
00569 .long vBANKCON6
00570 .long vBANKCON7
00571 .long vREFRESH
00572 .long vBANKSIZE
00573 .long vMRSRB6
00574 .long vMRSRB7
00575
00576 @ Processor clock values
00577 .align 4
00578 clock_locktime:
00579 .long vLOCKTIME
00580 @mpll_value:
00581 @ .long vMPLLCON_NOW
00582 mpll_value_USER:
00583 .long vMPLLCON_NOW_USER
00584 clkdivn_value:
00585 .long vCLKDIVN_NOW
00586
00587 @ initial values for serial
00588 uart_ulcon:
00589 .long vULCON
00590 uart_ucon:
00591 .long vUCON
00592 uart_ufcon:
00593 .long vUFCON
00594 uart_umcon:
00595 .long vUMCON
00596 @ inital values for GPIO
00597 gpio_con_uart:
00598 .long vGPHCON
00599 gpio_up_uart:
00600 .long vGPHUP
00601
00602 .align 2
00603 DW_STACK_START:
00604 .word STACK_BASE+STACK_SIZE-4
00605
00606 .align 4
00607 SerBase:
00608 @#if defined(CONFIG_SERIAL_UART0)
00609 .long UART0_CTL_BASE
00610 @#elif defined(CONFIG_SERIAL_UART1)
00611 @ .long UART1_CTL_BASE
00612 @#elif defined(CONFIG_SERIAL_UART2)
00613 @ .long UART2_CTL_BASE
00614 @#else
00615 @#error not defined base address of serial
00616 @#endif
00617
00618 #ifdef CONFIG_PMmultiple
00619 .align 4
00620 HandleReset:
00621 .long 0
00622 HandleUndef:
00623 .long 0
00624 HandleSWI:
00625 .long 0
00626 HandlePabort:
00627 .long 0
00628 HandleDabort:
00629 .long 0
00630 HandleReserved:
00631 .long 0
00632 HandleIRQ:
00633 .long 0
00634 HandleFIQ:
00635 .long 0
00636 PMCTL0_ADDR:
00637 .long 0x4c00000c
00638 PMCTL1_ADDR:
00639 .long 0x56000080
00640 PMST_ADDR:
00641 .long 0x560000B4
00642 PMSR0_ADDR:
00643 .long 0x560000B8
00644 REFR_ADDR:
00645 .long 0x48000024
00646 #endif
00647
00648 .align 4
00649 @ excption handle
00650 HandleReset: .long 0
00651 HandleUndef: .long 0
00652 HandleSWI: .long 0
00653 HandlePabort: .long 0
00654 HandleDabort: .long 0
00655 HandleReserved: .long 0
00656 HandleIRQ: .long 0
00657 HandleFIQ: .long 0
00658 @ irq handle
00659 HandleEINT0: .long 0
00660 HandleEINT1: .long 0
00661 HandleEINT2: .long 0
00662 HandleEINT3: .long 0
00663 HandleEINT4_7: .long 0
00664 HandleEINT8_23: .long 0
00665 HandleCAM: .long 0 @ Added for 2440.
00666 HandleBATFLT: .long 0
00667 HandleTICK: .long 0
00668 HandleWDT: .long 0
00669 HandleTimer0: .long 0
00670 HandleTimer1: .long 0
00671 HandleTimer2: .long 0
00672 HandleTimer3: .long 0
00673 HandleTimer4: .long 0
00674 HandleUART2: .long 0
00675 HandleLCD: .long 0
00676 HandleDMA0: .long 0
00677 HandleDMA1: .long 0
00678 HandleDMA2: .long 0
00679 HandleDMA3: .long 0
00680 HandleMMC: .long 0
00681 HandleSPI0: .long 0
00682 HandleUART1: .long 0
00683 HandleNFCON: .long 0 @ Added for 2440.
00684 HandleUSBD: .long 0
00685 HandleUSBH: .long 0
00686 HandleIIC: .long 0
00687 HandleUART0: .long 0
00688 HandleSPI1: .long 0
00689 HandleRTC: .long 0
00690 HandleADC: .long 0
00691
00692
00693
00694
