configbit.h

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/****************************************************************************************
*   File Name:      ConfigBit.h 
*
*   Copyright:
*
*   Description: For PIC18F87J10
*
*   History:
*
****************************************************************************************/
#ifndef _CONFIGBIT_H_
#define _CONFIGBIT_H_

// Configuration Bit Values

// Configuration register 1
// Extended PIC18 instruction set
 #define XINSTEN    0xFFFF  // Enabled 
 #define XINSTDIS   0xFFBF  // Disabled 
// Watchdog enable
 #define WDTDIS     0xFFFE & XINSTDIS   // Watchdog timer disabled 
 #define WDTEN      0xFFFF & XINSTDIS   // included only for completeness 
// Stack over/underflow reset enable
 #define STVREN     0xFFFF & XINSTDIS   // Stack over/underflow will cause reset 
 #define STVRDIS    0xFFDF & XINSTDIS   // Stack over/underflow will not cause reset 
// Background debugger
 #define DEBUGEN    0xFF7F & XINSTDIS   // Debugger enabled 
 #define DEBUGDIS   0xFFFF & XINSTDIS   // Debugger disabled 
// Code protection
 #define UNPROTECT  0xFFFF & XINSTDIS   // Do not protect memory 
 #define PROTECT    0xFBFF & XINSTDIS   // Protect code memory 

// Configuration register 2
// Oscillator settings
 #define ECPLL      0xFFFF  // EC with PLL when OSCON<1:0> = 00 
 #define EC     0xFFFE  // EC when OSCON<1:0> = 00 
 #define HSPLL      0xFFFD  // HS with PLL enabled when OSCON<1:0> = 00 
 #define HS     0xFFFC  // HS osc when OSCON<1:0> = 00 
 #define INTRC      0xFFFB  // INTRC when OSCON<1:0> = 00 
// Fail-Safe Clock Monitor Enable
 #define FCMDIS     0xFFBF  // Disabled 
 #define FCMEN      0xFFFF  // Enabled 
// Internal External Switch Over Mode
 #define IESODIS    0xFF7F  // Disabled 
 #define IESOEN     0xFFFF  // Enabled 
// Watchdog prescaler settings
 #define WDTPS32K   0xFFFF  // 1:32768 
 #define WDTPS16K   0xFEFF  // 1:16384 
 #define WDTPS8K    0xFDFF  // 1:8192 
 #define WDTPS4K    0xFCFF  // 1:4096 
 #define WDTPS2K    0xFBFF  // 1:2048 
 #define WDTPS1K    0xFAFF  // 1:1024 
 #define WDTPS512   0xF9FF  // 1:512 
 #define WDTPS256   0xF8FF  // 1:256 
 #define WDTPS128   0xF7FF  // 1:128 
 #define WDTPS64    0xF6FF  // 1:64 
 #define WDTPS32    0xF5FF  // 1:32 
 #define WDTPS16    0xF4FF  // 1:16 
 #define WDTPS8     0xF3FF  // 1:8 
 #define WDTPS4     0xF2FF  // 1:4 
 #define WDTPS2     0xF1FF  // 1:2 
 #define WDTPS1     0xF0FF  // 1:1 

// Configuration register 3
// External bus wait enable
#if defined(_18F85J10) || defined(_18F85J15) || defined(_18F86J10) || defined(_18F86J15) || defined(_18F87J10)
 #define WAITEN     0xFF7F  // WAIT states ofr external bus active 
 #define WAITDIS    0xFFFF  // WAIT states inactive 
// External memory bus configuration
 #define BW16       0xFFFF  // 16-Bit external data bus width 
 #define BW8        0xFFBF  // 8-Bit external data bus width 
// External Address bus width select
 #define ABW20      0xFFCF  // Extended microcontroller mode + 20-Bit address mode 
 #define ABW16      0xFFDF  // Extended microcontroller mode + 16-Bit address mode 
 #define ABW12      0xFFEF  // Extended microcontroller mode + 12-Bit address mode 
 #define ABW0       0xFFFF  // Microcontroller mode - no bus access 
 #define XMCU20     ABW20   // Deprecated
 #define XMCU16     ABW16   // Deprecated
 #define XMCU12     ABW12   // Deprecated
 #define MCU        ABW0    // Deprecated
// External address bus shift enable
 #define EASHFTEN   0xFFFF  // Enabled - addresses on external bus start at zero 
 #define EASHFTDIS  0xFFF7  // Disabled - address on external bus reflects PC 
#endif
// CCP2 Mux
 #define CCP2RC1    0xFFFF  // RC1 
 #define CCP2RE7    0xFEFF  // RE7 
// ECCP Mux
 #define ECCPRE     0xFFFF  // ECCP multiplexed on Port E 
 #define ECCPRH     0xFDFF  // ECCP multiplexed on Port H 


__CONFIG(1, UNPROTECT&DEBUGDIS&XINSTDIS&STVREN&WDTDIS);
__CONFIG(2, WAITDIS&WDTPS32K&IESOEN&FCMEN&HS);
__CONFIG(3, ECCPRE&CCP2RC1&BW16&ABW0&EASHFTEN);
//__CONFIG(4, );
//__CONFIG(5, UNPROTECT);
//__CONFIG(6, UNPROTECT);
//__CONFIG(7, UNPROTECT);

#endif

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