dma1.h

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/*************
*dma channel 0:unknow
*            1:sound
*            2:floppy
*            3:sound or LPT/ECP
*            4:dma-1 cascade through
*            5:unknown
*            6:unknown
*            7:sound
**************/
#ifndef DMA1_H
#define DMA1_H

#define DMA_WRITE 0
#define DMA_READ  1

//dma io base address definition
#define DMA1_BASE 0x00
//#define DMA2_BASE 0xc0

//dma registers definitions
#define DMA_CH0_ADDRESS    0x00 
#define DMA_CH0_COUNTER    0x01
#define DMA_CH1_ADDRESS    0x02
#define DMA_CH1_COUNTER    0x03
#define DMA_CH2_ADDRESS    0x04
#define DMA_CH2_COUNTER    0x05
#define DMA_CH3_ADDRESS    0x06
#define DMA_CH3_COUNTER    0x07
#define DMA_COMMAND_REG    0x08 //command register
#define DMA_STATUS_REG     0x08 //status register
#define DMA_REQUEST_REG    0x09 //request register
#define DMA_SINGLEMASK_REG 0x0a //mask register
#define DMA_MODE_REG       0x0b //mode register
#define DMA_FFRESET_REG    0x0c //clear internal flip flop
#define DMA_TEMP_REG       0x0d //temp register read only
#define DMA_SOFTRESET_REG  0x0d //software reset register write only
#define DMA_CLEARMASK_REG  0x0e //clear mask register
#define DMA_MASK_REG       0x0f //mask register

//mode register bit definitions
#define REQUEST_MODE 0x00
#define SINGLE_MODE  0x40
#define SEGMENT_MODE 0x80
#define CASCADE_MODE 0xc0

#define ADDRESS_INC 0x00
#define ADDRESS_DEC 0x20

#define AUTOLOAD_ENABLE  0x00
#define AUTOLOAD_DISABLE 0x10

#define TYPE_VERIFY  0x00
#define TYPE_READ    0x04
#define TYPE_WRITE   0x08
#define TYPE_INVALID 0x0c

#define DMA_CHANNEL0 0x00
#define DMA_CHANNEL1 0x01
#define DMA_CHANNEL2 0x02
#define DMA_CHANNEL3 0x03

//single mask register bit definitions
#define SINGLEMASK_SET      0x04
#define SINGLEMASK_CHANNEL0 0x00
#define SINGLEMASK_CHANNEL1 0x01
#define SINGLEMASK_CHANNEL2 0x02
#define SINGLEMASK_CHANNEL3 0x03

//mask register bit definitions
#define MASK_CH0_SET 0x01
#define MASK_CH1_SET 0x02
#define MASK_CH2_SET 0x03
#define MASK_CH3_SET 0x04

//request register bit definitions
#define REQUEST_SET 0x04
#define REQUEST_CHANNEL0 0x00
#define REQUEST_CHANNEL1 0x01
#define REQUEST_CHANNEL2 0x02
#define REQUEST_CHANNEL3 0x03

//status register bit definitions
#define STATUS_CH0_TC  0x01
#define STATUS_CH1_TC  0x02
#define STATUS_CH2_TC  0x04
#define STATUS_CH3_TC  0x08
#define STATUS_DMA0_TC 0x10
#define STATUS_DMA1_TC 0x20
#define STATUS_DMA2_TC 0x40
#define STATUS_DMA3_TC 0x80

//page register (74ls612)
#define DMA_CH0_PAGELOW  0x087
#define DMA_CH0_PAGEHIGH 0x487
#define DMA_CH1_PAGELOW  0x083
#define DMA_CH1_PAGEHIGH 0x483
#define DMA_CH2_PAGELOW  0x081
#define DMA_CH2_PAGEHIGH 0x481
#define DMA_CH3_PAGELOW  0x082
#define DMA_CH3_PAGEHIGH 0x482
#define DMA_CH4_PAGELOW  0x08f
#define DMA_CH4_PAGEHIGH 0x48f
#define DMA_CH5_PAGELOW  0x08b
#define DMA_CH5_PAGEHIGH 0x48b
#define DMA_CH6_PAGELOW  0x089
#define DMA_CH6_PAGEHIGH 0x489
#define DMA_CH7_PAGELOW  0x08a
#define DMA_CH7_PAGEHIGH 0x48a

#define DMA_OFFSET  0x04
#define DMA_LENGTH  0x05

void Dma1Init(void);
void Dma1EnableDma(U8 DmaChannel);
void Dma1DisableDma(U8 DmaChannel);
void Dma1ClearFlipflop(void);
void Dma1SetDmaAddress(U8 DmaChannelNumber,U32 Address);
void Dma1SetPage(U8 DmaChannelNumber,U16 PageNumber);
void Dma1SetDmaMode(U8 Channel,U8 Mode);
void Dma1SetDmaCount(U8 Channel,U16 Length);
void Dma1Transfer(U32 Address,U32 Length,U8 RwFlag,U8 DmaChannel);

#endif

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