arch/s3c2440/mmu.c File Reference

Go to the source code of this file.

Functions
static void	cpu_arm920_cache_clean_invalidate_all (void)
void	cache_clean_invalidate (void)
static void	cpu_arm920_tlb_invalidate_all (void)
void	MMU_SetFastBusMode (void)
void	MMU_SetAsyncBusMode (void)
void	tlb_invalidate (void)
static void	arm920_setup (void)
void	mmu_init (void)
static void	copy_vivi_to_ram (void)
static void	mem_mapping_linear (void)
static void	nor_flash_mapping (void)
static void	nor_flash_remapping (void)
void	mem_map_nand_boot (void)
void	mem_map_nor (void)
void	mem_map_init (void)
void	F_MmuInitial (void)
void	F_MemoryMapInitial (void)
Variables
static unsigned long *	mmu_tlb_base = (unsigned long *) MMU_TABLE_BASE

---

Function Documentation

static void arm920_setup

(

void

)

[inline, static]

Definition at line 87 of file mmu.c.

{
    unsigned long ttb = MMU_TABLE_BASE;

__asm__(
    /* Invalidate caches */
    "mov    r0, #0\n"
    "mcr    p15, 0, r0, c7, c7, 0\n"    /* invalidate I,D caches on v4 */
    "mcr    p15, 0, r0, c7, c10, 4\n"   /* drain write buffer on v4 */
    "mcr    p15, 0, r0, c8, c7, 0\n"    /* invalidate I,D TLBs on v4 */
    /* Load page table pointer */
    "mov    r4, %0\n"
    "mcr    p15, 0, r4, c2, c0, 0\n"    /* load page table pointer */
    /* Write domain id (cp15_r3) */
    "mvn    r0, #0\n"           /* Domains 0, 1 = client */
    "mcr    p15, 0, r0, c3, c0, 0\n"    /* load domain access register */
    /* Set control register v4 */
    "mrc    p15, 0, r0, c1, c0, 0\n"    /* get control register v4 */
    /* Clear out 'unwanted' bits (then put them in if we need them) */
                        /* .RVI ..RS B... .CAM */ 
    "bic    r0, r0, #0x3000\n"      /* ..11 .... .... .... */
    "bic    r0, r0, #0x0300\n"      /* .... ..11 .... .... */
    "bic    r0, r0, #0x0087\n"      /* .... .... 1... .111 */
    /* Turn on what we want */
    /* Fault checking enabled */
    "orr    r0, r0, #0x0002\n"      /* .... .... .... ..1. */
#ifdef CONFIG_CPU_D_CACHE_ON
    "orr    r0, r0, #0x0004\n"      /* .... .... .... .1.. */
#endif  
#ifdef CONFIG_CPU_I_CACHE_ON 
    "orr    r0, r0, #0x1000\n"      /* ...1 .... .... .... */
#endif  
    /* MMU enabled */
    "orr    r0, r0, #0x0001\n"      /* .... .... .... ...1 */
    "mcr    p15, 0, r0, c1, c0, 0\n"    /* write control register */
    : /* no outputs */
    : "r" (ttb) );
}

void cache_clean_invalidate

(

void

)

Definition at line 39 of file mmu.c.

{
    cpu_arm920_cache_clean_invalidate_all();
}

static void copy_vivi_to_ram

(

void

)

[static]

Definition at line 132 of file mmu.c.

{
    putstr_hex("Evacuating 1MB of Flash to DRAM at 0x", VIVI_RAM_BASE);
    memcpy((void *)VIVI_RAM_BASE, (void *)VIVI_ROM_BASE, VIVI_RAM_SIZE);
}

static void cpu_arm920_cache_clean_invalidate_all

(

void

)

[inline, static]

Definition at line 23 of file mmu.c.

{
__asm__(
    "   mov r1, #0\n"
    "   mov r1, #7 << 5\n"        /* 8 segments */
    "1: orr r3, r1, #63 << 26\n"      /* 64 entries */
    "2: mcr p15, 0, r3, c7, c14, 2\n" /* clean & invalidate D index */
    "   subs    r3, r3, #1 << 26\n"
    "   bcs 2b\n"             /* entries 64 to 0 */
    "   subs    r1, r1, #1 << 5\n"
    "   bcs 1b\n"             /* segments 7 to 0 */
    "   mcr p15, 0, r1, c7, c5, 0\n"  /* invalidate I cache */
    "   mcr p15, 0, r1, c7, c10, 4\n" /* drain WB */
    );
}

static void cpu_arm920_tlb_invalidate_all

(

void

)

[inline, static]

Definition at line 49 of file mmu.c.

{
    __asm__(
        "mov    r0, #0\n"
        "mcr    p15, 0, r0, c7, c10, 4\n"   /* drain WB */
        "mcr    p15, 0, r0, c8, c7, 0\n"    /* invalidate I & D TLBs */
        );
}

void F_MemoryMapInitial

(

void

)

Definition at line 229 of file mmu.c.

{
    mem_map_nand_boot();
    cache_clean_invalidate();
    tlb_invalidate();
}

void F_MmuInitial

(

void

)

Definition at line 225 of file mmu.c.

{
    arm920_setup();
}

void mem_map_init

(

void

)

Definition at line 215 of file mmu.c.

{
//#ifdef CONFIG_S3C2440_NAND_BOOT
    mem_map_nand_boot();
//#else
//  mem_map_nor();
//#endif
    cache_clean_invalidate();
    tlb_invalidate();
}

void mem_map_nand_boot

(

void

)

Definition at line 197 of file mmu.c.

{
    mem_mapping_linear();
#ifdef CONFIG_MTD_AMDSTD
    nor_flash_mapping();
#endif
}

void mem_map_nor

(

void

)

Definition at line 206 of file mmu.c.

{
    copy_vivi_to_ram();
    mem_mapping_linear();
    nor_flash_mapping();
    nor_flash_remapping();
}

static void mem_mapping_linear

(

void

)

[inline, static]

Definition at line 139 of file mmu.c.

{
    unsigned long pageoffset, sectionNumber;

    //putstr_hex("\n\r MMU table base address = 0x", (unsigned long)mmu_tlb_base);
    /* 4G  not cacacheable, not bufferable */
    for (sectionNumber = 0; sectionNumber < 4096; sectionNumber++) {
        pageoffset = (sectionNumber << 20);
        *(mmu_tlb_base + sectionNumber) = pageoffset | MMU_SECDESC;
    }

    /* make dram cacheable */
    for (pageoffset = DRAM_BASE; pageoffset < (DRAM_BASE+DRAM_SIZE); pageoffset += SZ_1M) {
        //DPRINTK(3, "Make DRAM section cacheable: 0x%08lx\n", pageoffset);
        *(mmu_tlb_base + (pageoffset >> 20)) = pageoffset | MMU_SECDESC | MMU_CACHEABLE; 
    }
}

void mmu_init

(

void

)

Definition at line 126 of file mmu.c.

{
    arm920_setup();
}

void MMU_SetAsyncBusMode

(

void

)

Definition at line 71 of file mmu.c.

{
    __asm__(
        "mrc    p15, 0, r0, c1, c0, #0\n"
        "orr    r0, r0, #( 3 << 30 )\n"
        "mcr    p15, 0, r0, c1, c0, 0 \n"
           );
}

void MMU_SetFastBusMode

(

void

)

Definition at line 61 of file mmu.c.

{
    /* R1_nF|R1_iA */
    __asm__(
        "mrc    p15, 0, r0, c1, c0, #0\n"
        "bic    r0, r0, #( 3 << 30 )\n"
        "mcr    p15, 0, r0, c1, c0, 0 \n"
           );
}

static void nor_flash_mapping

(

void

)

[inline, static]

Definition at line 158 of file mmu.c.

{
    unsigned long offset, cached_addr, uncached_addr;

    cached_addr = FLASH_BASE;
    uncached_addr = FLASH_UNCACHED_BASE;

    /*for (offset = 0; offset < FLASH_SIZE; offset += MMU_SECTION_SIZE) { 
        cached_addr += offset;
        uncached_addr += offset;
        *(mmu_tlb_base + (cached_addr >> 20)) = \
                (cached_addr | MMU_SECDESC | MMU_CACHEABLE);
        *(mmu_tlb_base + (uncached_addr >> 20)) = \
                (cached_addr | MMU_SECDESC);
    }*/

    for (offset = 0; offset < FLASH_SIZE; offset += MMU_SECTION_SIZE) { 
        cached_addr = FLASH_BASE + offset;
        uncached_addr = FLASH_UNCACHED_BASE + offset;
        *(mmu_tlb_base + (cached_addr >> 20)) = \
                (cached_addr | MMU_SECDESC | MMU_CACHEABLE);
        *(mmu_tlb_base + (uncached_addr >> 20)) = \
                (cached_addr | MMU_SECDESC);
    }
}

static void nor_flash_remapping

(

void

)

[inline, static]

Definition at line 189 of file mmu.c.

{
    putstr_hex("Map flash virtual section to DRAM at 0x", VIVI_RAM_BASE);
    *(mmu_tlb_base + (VIVI_ROM_BASE >> 20)) = \
                (VIVI_RAM_BASE | MMU_SECDESC | MMU_CACHEABLE);
}

void tlb_invalidate

(

void

)

Definition at line 82 of file mmu.c.

{
    cpu_arm920_tlb_invalidate_all();
}

---

Variable Documentation

unsigned long* mmu_tlb_base = (unsigned long *) MMU_TABLE_BASE [static]

Definition at line 15 of file mmu.c.